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authorEvan Cheng <evan.cheng@apple.com>2007-06-08 21:59:56 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-06-08 21:59:56 +0000
commitbfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8 (patch)
tree466f212b5d912a839f160486256a40f008202b69 /include/llvm/Target/TargetInstrInfo.h
parent61718a6285a4f140cab530bcc07c6492902dc710 (diff)
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Add a utility routine to check for unpredicated terminator instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/Target/TargetInstrInfo.h')
-rw-r--r--include/llvm/Target/TargetInstrInfo.h8
1 files changed, 6 insertions, 2 deletions
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index f03fbb5..2571db4 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -399,19 +399,23 @@ public:
abort();
}
- /// isPredicable - Returns true if the instruction is already predicated.
+ /// isPredicated - Returns true if the instruction is already predicated.
///
virtual bool isPredicated(const MachineInstr *MI) const {
return false;
}
+ /// isUnpredicatedTerminator - Returns true if the instruction is a
+ /// terminator instruction that has not been predicated.
+ bool isUnpredicatedTerminator(const MachineInstr *MI) const;
+
/// PredicateInstruction - Convert the instruction into a predicated
/// instruction. It returns true if the operation was successful.
virtual
bool PredicateInstruction(MachineInstr *MI,
const std::vector<MachineOperand> &Pred) const;
- /// SubsumesPredicate - Returns true if the first specified predicated
+ /// SubsumesPredicate - Returns true if the first specified predicate
/// subsumes the second, e.g. GE subsumes GT.
virtual
bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,