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author | Evan Cheng <evan.cheng@apple.com> | 2007-07-10 18:06:29 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2007-07-10 18:06:29 +0000 |
commit | ed80ef6089ef83bd1c79f1477d7a12a949474af5 (patch) | |
tree | f76b4b3054d3ee871e0ae38da93e35f36881c193 /include/llvm/Target/TargetInstrInfo.h | |
parent | 88cc092ca5bd79480205ee7b01aa39c13f3e35d7 (diff) | |
download | external_llvm-ed80ef6089ef83bd1c79f1477d7a12a949474af5.zip external_llvm-ed80ef6089ef83bd1c79f1477d7a12a949474af5.tar.gz external_llvm-ed80ef6089ef83bd1c79f1477d7a12a949474af5.tar.bz2 |
Add OptionalDefOperand. Remove clobbersPred. Also add DefinesPredicate to be used by if-converter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38499 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/Target/TargetInstrInfo.h')
-rw-r--r-- | include/llvm/Target/TargetInstrInfo.h | 30 |
1 files changed, 21 insertions, 9 deletions
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 9a8e3b4..25fb79f 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -82,13 +82,13 @@ const unsigned M_PREDICABLE = 1 << 12; // at any time, e.g. constant generation, load from constant pool. const unsigned M_REMATERIALIZIBLE = 1 << 13; -// M_CLOBBERS_PRED - Set if this instruction may clobbers the condition code -// register and / or registers that are used to predicate instructions. -const unsigned M_CLOBBERS_PRED = 1 << 14; - // M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated. // (e.g. instructions with unique labels attached). -const unsigned M_NOT_DUPLICABLE = 1 << 15; +const unsigned M_NOT_DUPLICABLE = 1 << 14; + +// M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g. +// ARM instructions which can set condition code if 's' bit is set. +const unsigned M_HAS_OPTIONAL_DEF = 1 << 15; // Machine operand flags // M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it @@ -99,6 +99,10 @@ const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0; /// predicate operand that controls an M_PREDICATED instruction. const unsigned M_PREDICATE_OPERAND = 1 << 1; +/// M_OPTIONAL_DEF_OPERAND - Set if this operand is a optional def. +/// +const unsigned M_OPTIONAL_DEF_OPERAND = 1 << 2; + namespace TOI { // Operand constraints: only "tied_to" for now. enum OperandConstraint { @@ -264,14 +268,14 @@ public: return get(Opcode).Flags & M_PREDICABLE; } - bool clobbersPredicate(MachineOpCode Opcode) const { - return get(Opcode).Flags & M_CLOBBERS_PRED; - } - bool isNotDuplicable(MachineOpCode Opcode) const { return get(Opcode).Flags & M_NOT_DUPLICABLE; } + bool hasOptionalDef(MachineOpCode Opcode) const { + return get(Opcode).Flags & M_HAS_OPTIONAL_DEF; + } + /// isTriviallyReMaterializable - Return true if the instruction is trivially /// rematerializable, meaning it has no side effects and requires no operands /// that aren't always available. @@ -452,6 +456,14 @@ public: return false; } + /// DefinesPredicate - If the specified instruction defines any predicate + /// or condition code register(s) used for predication, returns true as well + /// as the definition predicate(s) by reference. + virtual bool DefinesPredicate(MachineInstr *MI, + std::vector<MachineOperand> &Pred) const { + return false; + } + /// getPointerRegClass - Returns a TargetRegisterClass used for pointer /// values. virtual const TargetRegisterClass *getPointerRegClass() const { |