Fixed up comments in TargetLowering.h to conform to the LLVM Style Guide.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186121 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 613 insertions, 682 deletions

diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index d1c98f6..09a93f9 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -6,17 +6,18 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
-//
-// This file describes how to lower LLVM code to machine code.  This has two
-// main components:
-//
-//  1. Which ValueTypes are natively supported by the target.
-//  2. Which operations are supported for supported ValueTypes.
-//  3. Cost thresholds for alternative implementations of certain operations.
-//
-// In addition it has a few other components, like information about FP
-// immediates.
-//
+///
+/// \file
+/// This file describes how to lower LLVM code to machine code.  This has two
+/// main components:
+///
+///  1. Which ValueTypes are natively supported by the target.
+///  2. Which operations are supported for supported ValueTypes.
+///  3. Cost thresholds for alternative implementations of certain operations.
+///
+/// In addition it has a few other components, like information about FP
+/// immediates.
+///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TARGET_TARGETLOWERING_H
@@ -67,15 +68,15 @@ namespace llvm {
     };
   }
 
-/// TargetLoweringBase - This base class for TargetLowering contains the
-/// SelectionDAG-independent parts that can be used from the rest of CodeGen.
+/// This base class for TargetLowering contains the SelectionDAG-independent
+/// parts that can be used from the rest of CodeGen.
 class TargetLoweringBase {
   TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
   void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
 
 public:
-  /// LegalizeAction - This enum indicates whether operations are valid for a
-  /// target, and if not, what action should be used to make them valid.
+  /// This enum indicates whether operations are valid for a target, and if not,
+  /// what action should be used to make them valid.
   enum LegalizeAction {
     Legal,      // The target natively supports this operation.
     Promote,    // This operation should be executed in a larger type.
@@ -83,8 +84,8 @@ public:
     Custom      // Use the LowerOperation hook to implement custom lowering.
   };
 
-  /// LegalizeTypeAction - This enum indicates whether a types are legal for a
-  /// target, and if not, what action should be used to make them valid.
+  /// This enum indicates whether a types are legal for a target, and if not,
+  /// what action should be used to make them valid.
   enum LegalizeTypeAction {
     TypeLegal,           // The target natively supports this type.
     TypePromoteInteger,  // Replace this integer with a larger one.
@@ -100,12 +101,14 @@ public:
   /// in order to type-legalize it.
   typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
 
-  enum BooleanContent { // How the target represents true/false values.
+  /// Enum that describes how the target represents true/false values.
+  enum BooleanContent {
     UndefinedBooleanContent,    // Only bit 0 counts, the rest can hold garbage.
     ZeroOrOneBooleanContent,        // All bits zero except for bit 0.
     ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
   };
 
+  /// Enum that describes what type of support for selects the target has.
   enum SelectSupportKind {
     ScalarValSelect,      // The target supports scalar selects (ex: cmov).
     ScalarCondVectorVal,  // The target supports selects with a scalar condition
@@ -153,112 +156,111 @@ public:
 
   EVT getShiftAmountTy(EVT LHSTy) const;
 
-  /// isSelectExpensive - Return true if the select operation is expensive for
-  /// this target.
+  /// Return true if the select operation is expensive for this target.
   bool isSelectExpensive() const { return SelectIsExpensive; }
 
   virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
     return true;
   }
 
-  /// shouldSplitVectorElementType - Return true if a vector of the given type
-  /// should be split (TypeSplitVector) instead of promoted
-  /// (TypePromoteInteger) during type legalization.
+  /// Return true if a vector of the given type should be split
+  /// (TypeSplitVector) instead of promoted (TypePromoteInteger) during type
+  /// legalization.
   virtual bool shouldSplitVectorElementType(EVT /*VT*/) const { return false; }
 
-  /// isIntDivCheap() - Return true if integer divide is usually cheaper than
-  /// a sequence of several shifts, adds, and multiplies for this target.
+  /// Return true if integer divide is usually cheaper than a sequence of
+  /// several shifts, adds, and multiplies for this target.
   bool isIntDivCheap() const { return IntDivIsCheap; }
 
-  /// isSlowDivBypassed - Returns true if target has indicated at least one
-  /// type should be bypassed.
+  /// Returns true if target has indicated at least one type should be bypassed.
   bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
 
-  /// getBypassSlowDivTypes - Returns map of slow types for division or
-  /// remainder with corresponding fast types
+  /// Returns map of slow types for division or remainder with corresponding
+  /// fast types
   const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
     return BypassSlowDivWidths;
   }
 
-  /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
-  /// srl/add/sra.
+  /// Return true if pow2 div is cheaper than a chain of srl/add/sra.
   bool isPow2DivCheap() const { return Pow2DivIsCheap; }
 
-  /// isJumpExpensive() - Return true if Flow Control is an expensive operation
-  /// that should be avoided.
+  /// Return true if Flow Control is an expensive operation that should be
+  /// avoided.
   bool isJumpExpensive() const { return JumpIsExpensive; }
 
-  /// isPredictableSelectExpensive - Return true if selects are only cheaper
-  /// than branches if the branch is unlikely to be predicted right.
+  /// Return true if selects are only cheaper than branches if the branch is
+  /// unlikely to be predicted right.
   bool isPredictableSelectExpensive() const {
     return PredictableSelectIsExpensive;
   }
 
-  /// getSetCCResultType - Return the ValueType of the result of SETCC
-  /// operations.  Also used to obtain the target's preferred type for
-  /// the condition operand of SELECT and BRCOND nodes.  In the case of
-  /// BRCOND the argument passed is MVT::Other since there are no other
-  /// operands to get a type hint from.
+  /// Return the ValueType of the result of SETCC operations.  Also used to
+  /// obtain the target's preferred type for the condition operand of SELECT and
+  /// BRCOND nodes.  In the case of BRCOND the argument passed is MVT::Other
+  /// since there are no other operands to get a type hint from.
   virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
 
-  /// getCmpLibcallReturnType - Return the ValueType for comparison
-  /// libcalls. Comparions libcalls include floating point comparion calls,
-  /// and Ordered/Unordered check calls on floating point numbers.
+  /// Return the ValueType for comparison libcalls. Comparions libcalls include
+  /// floating point comparion calls, and Ordered/Unordered check calls on
+  /// floating point numbers.
   virtual
   MVT::SimpleValueType getCmpLibcallReturnType() const;
 
-  /// getBooleanContents - For targets without i1 registers, this gives the
-  /// nature of the high-bits of boolean values held in types wider than i1.
+  /// For targets without i1 registers, this gives the nature of the high-bits
+  /// of boolean values held in types wider than i1.
+  ///
   /// "Boolean values" are special true/false values produced by nodes like
   /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
-  /// Not to be confused with general values promoted from i1.
-  /// Some cpus distinguish between vectors of boolean and scalars; the isVec
-  /// parameter selects between the two kinds.  For example on X86 a scalar
-  /// boolean should be zero extended from i1, while the elements of a vector
-  /// of booleans should be sign extended from i1.
+  /// Not to be confused with general values promoted from i1.  Some cpus
+  /// distinguish between vectors of boolean and scalars; the isVec parameter
+  /// selects between the two kinds.  For example on X86 a scalar boolean should
+  /// be zero extended from i1, while the elements of a vector of booleans
+  /// should be sign extended from i1.
   BooleanContent getBooleanContents(bool isVec) const {
     return isVec ? BooleanVectorContents : BooleanContents;
   }
 
-  /// getSchedulingPreference - Return target scheduling preference.
+  /// Return target scheduling preference.
   Sched::Preference getSchedulingPreference() const {
     return SchedPreferenceInfo;
   }
 
-  /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to
-  /// different scheduling heuristics for different nodes. This function returns
-  /// the preference (or none) for the given node.
+  /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
+  /// for different nodes. This function returns the preference (or none) for
+  /// the given node.
   virtual Sched::Preference getSchedulingPreference(SDNode *) const {
     return Sched::None;
   }
 
-  /// getRegClassFor - Return the register class that should be used for the
-  /// specified value type.
+  /// Return the register class that should be used for the specified value
+  /// type.
   virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
     const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
     assert(RC && "This value type is not natively supported!");
     return RC;
   }
 
-  /// getRepRegClassFor - Return the 'representative' register class for the
-  /// specified value type. The 'representative' register class is the largest
-  /// legal super-reg register class for the register class of the value type.
-  /// For example, on i386 the rep register class for i8, i16, and i32 are GR32;
-  /// while the rep register class is GR64 on x86_64.
+  /// Return the 'representative' register class for the specified value
+  /// type.
+  ///
+  /// The 'representative' register class is the largest legal super-reg
+  /// register class for the register class of the value type.  For example, on
+  /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
+  /// register class is GR64 on x86_64.
   virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
     const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
     return RC;
   }
 
-  /// getRepRegClassCostFor - Return the cost of the 'representative' register
-  /// class for the specified value type.
+  /// Return the cost of the 'representative' register class for the specified
+  /// value type.
   virtual uint8_t getRepRegClassCostFor(MVT VT) const {
     return RepRegClassCostForVT[VT.SimpleTy];
   }
 
-  /// isTypeLegal - Return true if the target has native support for the
-  /// specified value type.  This means that it has a register that directly
-  /// holds it without promotions or expansions.
+  /// Return true if the target has native support for the specified value type.
+  /// This means that it has a register that directly holds it without
+  /// promotions or expansions.
   bool isTypeLegal(EVT VT) const {
     assert(!VT.isSimple() ||
            (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
@@ -289,10 +291,10 @@ public:
     return ValueTypeActions;
   }
 
-  /// getTypeAction - Return how we should legalize values of this type, either
-  /// it is already legal (return 'Legal') or we need to promote it to a larger
-  /// type (return 'Promote'), or we need to expand it into multiple registers
-  /// of smaller integer type (return 'Expand').  'Custom' is not an option.
+  /// Return how we should legalize values of this type, either it is already
+  /// legal (return 'Legal') or we need to promote it to a larger type (return
+  /// 'Promote'), or we need to expand it into multiple registers of smaller
+  /// integer type (return 'Expand').  'Custom' is not an option.
   LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
     return getTypeConversion(Context, VT).first;
   }
@@ -300,20 +302,20 @@ public:
     return ValueTypeActions.getTypeAction(VT);
   }
 
-  /// getTypeToTransformTo - For types supported by the target, this is an
-  /// identity function.  For types that must be promoted to larger types, this
-  /// returns the larger type to promote to.  For integer types that are larger
-  /// than the largest integer register, this contains one step in the expansion
-  /// to get to the smaller register. For illegal floating point types, this
-  /// returns the integer type to transform to.
+  /// For types supported by the target, this is an identity function.  For
+  /// types that must be promoted to larger types, this returns the larger type
+  /// to promote to.  For integer types that are larger than the largest integer
+  /// register, this contains one step in the expansion to get to the smaller
+  /// register. For illegal floating point types, this returns the integer type
+  /// to transform to.
   EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
     return getTypeConversion(Context, VT).second;
   }
 
-  /// getTypeToExpandTo - For types supported by the target, this is an
-  /// identity function.  For types that must be expanded (i.e. integer types
-  /// that are larger than the largest integer register or illegal floating
-  /// point types), this returns the largest legal type it will be expanded to.
+  /// For types supported by the target, this is an identity function.  For
+  /// types that must be expanded (i.e. integer types that are larger than the
+  /// largest integer register or illegal floating point types), this returns
+  /// the largest legal type it will be expanded to.
   EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
     assert(!VT.isVector());
     while (true) {
@@ -329,24 +331,19 @@ public:
     }
   }
 
-  /// getVectorTypeBreakdown - Vector types are broken down into some number of
-  /// legal first class types.  For example, EVT::v8f32 maps to 2 EVT::v4f32
-  /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
-  /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
+  /// Vector types are broken down into some number of legal first class types.
+  /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
+  /// promoted EVT::f64 values with the X86 FP stack.  Similarly, EVT::v2i64
+  /// turns into 4 EVT::i32 values with both PPC and X86.
   ///
   /// This method returns the number of registers needed, and the VT for each
   /// register.  It also returns the VT and quantity of the intermediate values
   /// before they are promoted/expanded.
-  ///
   unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
                                   EVT &IntermediateVT,
                                   unsigned &NumIntermediates,
                                   MVT &RegisterVT) const;
 
-  /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
-  /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
-  /// this is the case, it returns true and store the intrinsic
-  /// information into the IntrinsicInfo that was passed to the function.
   struct IntrinsicInfo {
     unsigned     opc;         // target opcode
     EVT          memVT;       // memory VT
@@ -358,45 +355,48 @@ public:
     bool         writeMem;    // writes memory?
   };
 
+  /// Given an intrinsic, checks if on the target the intrinsic will need to map
+  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
+  /// true and store the intrinsic information into the IntrinsicInfo that was
+  /// passed to the function.
   virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
                                   unsigned /*Intrinsic*/) const {
     return false;
   }
 
-  /// isFPImmLegal - Returns true if the target can instruction select the
-  /// specified FP immediate natively. If false, the legalizer will materialize
-  /// the FP immediate as a load from a constant pool.
+  /// Returns true if the target can instruction select the specified FP
+  /// immediate natively. If false, the legalizer will materialize the FP
+  /// immediate as a load from a constant pool.
   virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
     return false;
   }
 
-  /// isShuffleMaskLegal - Targets can use this to indicate that they only
-  /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
-  /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
-  /// are assumed to be legal.
+  /// Targets can use this to indicate that they only support *some*
+  /// VECTOR_SHUFFLE operations, those with specific masks.  By default, if a
+  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
+  /// legal.
   virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
                                   EVT /*VT*/) const {
     return true;
   }
 
-  /// canOpTrap - Returns true if the operation can trap for the value type.
+  /// Returns true if the operation can trap for the value type.
+  ///
   /// VT must be a legal type. By default, we optimistically assume most
   /// operations don't trap except for divide and remainder.
   virtual bool canOpTrap(unsigned Op, EVT VT) const;
 
-  /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
-  /// used by Targets can use this to indicate if there is a suitable
-  /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
-  /// pool entry.
+  /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
+  /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
+  /// a VAND with a constant pool entry.
   virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
                                       EVT /*VT*/) const {
     return false;
   }
 
-  /// getOperationAction - Return how this operation should be treated: either
-  /// it is legal, needs to be promoted to a larger size, needs to be
-  /// expanded to some other code sequence, or the target has a custom expander
-  /// for it.
+  /// Return how this operation should be treated: either it is legal, needs to
+  /// be promoted to a larger size, needs to be expanded to some other code
+  /// sequence, or the target has a custom expander for it.
   LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
     if (VT.isExtended()) return Expand;
     // If a target-specific SDNode requires legalization, require the target
@@ -406,59 +406,55 @@ public:
     return (LegalizeAction)OpActions[I][Op];
   }
 
-  /// isOperationLegalOrCustom - Return true if the specified operation is
-  /// legal on this target or can be made legal with custom lowering. This
-  /// is used to help guide high-level lowering decisions.
+  /// Return true if the specified operation is legal on this target or can be
+  /// made legal with custom lowering. This is used to help guide high-level
+  /// lowering decisions.
   bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
     return (VT == MVT::Other || isTypeLegal(VT)) &&
       (getOperationAction(Op, VT) == Legal ||
        getOperationAction(Op, VT) == Custom);
   }
 
-  /// isOperationLegalOrPromote - Return true if the specified operation is
-  /// legal on this target or can be made legal using promotion. This
-  /// is used to help guide high-level lowering decisions.
+  /// Return true if the specified operation is legal on this target or can be
+  /// made legal using promotion. This is used to help guide high-level lowering
+  /// decisions.
   bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
     return (VT == MVT::Other || isTypeLegal(VT)) &&
       (getOperationAction(Op, VT) == Legal ||
        getOperationAction(Op, VT) == Promote);
   }
 
-  /// isOperationExpand - Return true if the specified operation is illegal on
-  /// this target or unlikely to be made legal with custom lowering. This is
-  /// used to help guide high-level lowering decisions.
+  /// Return true if the specified operation is illegal on this target or
+  /// unlikely to be made legal with custom lowering. This is used to help guide
+  /// high-level lowering decisions.
   bool isOperationExpand(unsigned Op, EVT VT) const {
     return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
   }
 
-  /// isOperationLegal - Return true if the specified operation is legal on this
-  /// target.
+  /// Return true if the specified operation is legal on this target.
   bool isOperationLegal(unsigned Op, EVT VT) const {
     return (VT == MVT::Other || isTypeLegal(VT)) &&
            getOperationAction(Op, VT) == Legal;
   }
 
-  /// getLoadExtAction - Return how this load with extension should be treated:
-  /// either it is legal, needs to be promoted to a larger size, needs to be
-  /// expanded to some other code sequence, or the target has a custom expander
-  /// for it.
+  /// Return how this load with extension should be treated: either it is legal,
+  /// needs to be promoted to a larger size, needs to be expanded to some other
+  /// code sequence, or the target has a custom expander for it.
   LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const {
     assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
            "Table isn't big enough!");
     return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType];
   }
 
-  /// isLoadExtLegal - Return true if the specified load with extension is legal
-  /// on this target.
+  /// Return true if the specified load with extension is legal on this target.
   bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
     return VT.isSimple() &&
       getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
   }
 
-  /// getTruncStoreAction - Return how this store with truncation should be
-  /// treated: either it is legal, needs to be promoted to a larger size, needs
-  /// to be expanded to some other code sequence, or the target has a custom
-  /// expander for it.
+  /// Return how this store with truncation should be treated: either it is
+  /// legal, needs to be promoted to a larger size, needs to be expanded to some
+  /// other code sequence, or the target has a custom expander for it.
   LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const {
     assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
            "Table isn't big enough!");
@@ -466,17 +462,16 @@ public:
                                             [MemVT.SimpleTy];
   }
 
-  /// isTruncStoreLegal - Return true if the specified store with truncation is
-  /// legal on this target.
+  /// Return true if the specified store with truncation is legal on this
+  /// target.
   bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
     return isTypeLegal(ValVT) && MemVT.isSimple() &&
       getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
   }
 
-  /// getIndexedLoadAction - Return how the indexed load should be treated:
-  /// either it is legal, needs to be promoted to a larger size, needs to be
-  /// expanded to some other code sequence, or the target has a custom expander
-  /// for it.
+  /// Return how the indexed load should be treated: either it is legal, needs
+  /// to be promoted to a larger size, needs to be expanded to some other code
+  /// sequence, or the target has a custom expander for it.
   LegalizeAction
   getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
     assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
@@ -485,18 +480,16 @@ public:
     return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
   }
 
-  /// isIndexedLoadLegal - Return true if the specified indexed load is legal
-  /// on this target.
+  /// Return true if the specified indexed load is legal on this target.
   bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
     return VT.isSimple() &&
       (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
        getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
   }
 
-  /// getIndexedStoreAction - Return how the indexed store should be treated:
-  /// either it is legal, needs to be promoted to a larger size, needs to be
-  /// expanded to some other code sequence, or the target has a custom expander
-  /// for it.
+  /// Return how the indexed store should be treated: either it is legal, needs
+  /// to be promoted to a larger size, needs to be expanded to some other code
+  /// sequence, or the target has a custom expander for it.
   LegalizeAction
   getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
     assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
@@ -505,17 +498,16 @@ public:
     return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
   }
 
-  /// isIndexedStoreLegal - Return true if the specified indexed load is legal
-  /// on this target.
+  /// Return true if the specified indexed load is legal on this target.
   bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
     return VT.isSimple() &&
       (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
        getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
   }
 
-  /// getCondCodeAction - Return how the condition code should be treated:
-  /// either it is legal, needs to be expanded to some other code sequence,
-  /// or the target has a custom expander for it.
+  /// Return how the condition code should be treated: either it is legal, needs
+  /// to be expanded to some other code sequence, or the target has a custom
+  /// expander for it.
   LegalizeAction
   getCondCodeAction(ISD::CondCode CC, MVT VT) const {
     assert((unsigned)CC < array_lengthof(CondCodeActions) &&
@@ -530,8 +522,7 @@ public:
     return Action;
   }
 
-  /// isCondCodeLegal - Return true if the specified condition code is legal
-  /// on this target.
+  /// Return true if the specified condition code is legal on this target.
   bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
     return
       getCondCodeAction(CC, VT) == Legal ||
@@ -539,8 +530,8 @@ public:
   }
 
 
-  /// getTypeToPromoteTo - If the action for this operation is to promote, this
-  /// method returns the ValueType to promote to.
+  /// If the action for this operation is to promote, this method returns the
+  /// ValueType to promote to.
   MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
     assert(getOperationAction(Op, VT) == Promote &&
            "This operation isn't promoted!");
@@ -564,10 +555,10 @@ public:
     return NVT;
   }
 
-  /// getValueType - Return the EVT corresponding to this LLVM type.
-  /// This is fixed by the LLVM operations except for the pointer size.  If
-  /// AllowUnknown is true, this will return MVT::Other for types with no EVT
-  /// counterpart (e.g. structs), otherwise it will assert.
+  /// Return the EVT corresponding to this LLVM type.  This is fixed by the LLVM
+  /// operations except for the pointer size.  If AllowUnknown is true, this
+  /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
+  /// otherwise it will assert.
   EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
     // Lower scalar pointers to native pointer types.
     if (Ty->isPointerTy()) return PointerTy;
@@ -589,20 +580,17 @@ public:
     return getValueType(Ty, AllowUnknown).getSimpleVT();
   }
 
-  /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
-  /// function arguments in the caller parameter area.  This is the actual
-  /// alignment, not its logarithm.
+  /// Return the desired alignment for ByVal aggregate function arguments in the
+  /// caller parameter area.  This is the actual alignment, not its logarithm.
   virtual unsigned getByValTypeAlignment(Type *Ty) const;
 
-  /// getRegisterType - Return the type of registers that this ValueType will
-  /// eventually require.
+  /// Return the type of registers that this ValueType will eventually require.
   MVT getRegisterType(MVT VT) const {
     assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
     return RegisterTypeForVT[VT.SimpleTy];
   }
 
-  /// getRegisterType - Return the type of registers that this ValueType will
-  /// eventually require.
+  /// Return the type of registers that this ValueType will eventually require.
   MVT getRegisterType(LLVMContext &Context, EVT VT) const {
     if (VT.isSimple()) {
       assert((unsigned)VT.getSimpleVT().SimpleTy <
@@ -623,12 +611,14 @@ public:
     llvm_unreachable("Unsupported extended type!");
   }
 
-  /// getNumRegisters - Return the number of registers that this ValueType will
-  /// eventually require.  This is one for any types promoted to live in larger
-  /// registers, but may be more than one for types (like i64) that are split
-  /// into pieces.  For types like i140, which are first promoted then expanded,
-  /// it is the number of registers needed to hold all the bits of the original
-  /// type.  For an i140 on a 32 bit machine this means 5 registers.
+  /// Return the number of registers that this ValueType will eventually
+  /// require.
+  ///
+  /// This is one for any types promoted to live in larger registers, but may be
+  /// more than one for types (like i64) that are split into pieces.  For types
+  /// like i140, which are first promoted then expanded, it is the number of
+  /// registers needed to hold all the bits of the original type.  For an i140
+  /// on a 32 bit machine this means 5 registers.
   unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
     if (VT.isSimple()) {
       assert((unsigned)VT.getSimpleVT().SimpleTy <
@@ -649,68 +639,72 @@ public:
     llvm_unreachable("Unsupported extended type!");
   }
 
-  /// ShouldShrinkFPConstant - If true, then instruction selection should
-  /// seek to shrink the FP constant of the specified type to a smaller type
-  /// in order to save space and / or reduce runtime.
+  /// If true, then instruction selection should seek to shrink the FP constant
+  /// of the specified type to a smaller type in order to save space and / or
+  /// reduce runtime.
   virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
 
-  /// hasTargetDAGCombine - If true, the target has custom DAG combine
-  /// transformations that it can perform for the specified node.
+  /// If true, the target has custom DAG combine transformations that it can
+  /// perform for the specified node.
   bool hasTargetDAGCombine(ISD::NodeType NT) const {
     assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
     return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
   }
 
+  /// \brief Get maximum # of store operations permitted for llvm.memset
+  ///
   /// This function returns the maximum number of store operations permitted
   /// to replace a call to llvm.memset. The value is set by the target at the
   /// performance threshold for such a replacement. If OptSize is true,
   /// return the limit for functions that have OptSize attribute.
-  /// @brief Get maximum # of store operations permitted for llvm.memset
   unsigned getMaxStoresPerMemset(bool OptSize) const {
     return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
   }
 
+  /// \brief Get maximum # of store operations permitted for llvm.memcpy
+  ///
   /// This function returns the maximum number of store operations permitted
   /// to replace a call to llvm.memcpy. The value is set by the target at the
   /// performance threshold for such a replacement. If OptSize is true,
   /// return the limit for functions that have OptSize attribute.
-  /// @brief Get maximum # of store operations permitted for llvm.memcpy
   unsigned getMaxStoresPerMemcpy(bool OptSize) const {
     return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
   }
 
+  /// \brief Get maximum # of store operations permitted for llvm.memmove
+  ///
   /// This function returns the maximum number of store operations permitted
   /// to replace a call to llvm.memmove. The value is set by the target at the
   /// performance threshold for such a replacement. If OptSize is true,
   /// return the limit for functions that have OptSize attribute.
-  /// @brief Get maximum # of store operations permitted for llvm.memmove
   unsigned getMaxStoresPerMemmove(bool OptSize) const {
     return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
   }
 
+  /// \brief Determine if the target supports unaligned memory accesses.
+  ///
   /// This function returns true if the target allows unaligned memory accesses.
   /// of the specified type. If true, it also returns whether the unaligned
   /// memory access is "fast" in the second argument by reference. This is used,
-  /// for example, in situations where an array copy/move/set is  converted to a
+  /// for example, in situations where an array copy/move/set is converted to a
   /// sequence of store operations. It's use helps to ensure that such
-  /// replacements don't generate code that causes an alignment error  (trap) on
+  /// replacements don't generate code that causes an alignment error (trap) on
   /// the target machine.
-  /// @brief Determine if the target supports unaligned memory accesses.
   virtual bool allowsUnalignedMemoryAccesses(EVT, bool * /*Fast*/ = 0) const {
     return false;
   }
 
-  /// getOptimalMemOpType - Returns the target specific optimal type for load
-  /// and store operations as a result of memset, memcpy, and memmove
-  /// lowering. If DstAlign is zero that means it's safe to destination
-  /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
-  /// means there isn't a need to check it against alignment requirement,
-  /// probably because the source does not need to be loaded. If 'IsMemset' is
-  /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
-  /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
-  /// source is constant so it does not need to be loaded.
-  /// It returns EVT::Other if the type should be determined using generic
-  /// target-independent logic.
+  /// Returns the target specific optimal type for load and store operations as
+  /// a result of memset, memcpy, and memmove lowering.
+  ///
+  /// If DstAlign is zero that means it's safe to destination alignment can
+  /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
+  /// a need to check it against alignment requirement, probably because the
+  /// source does not need to be loaded. If 'IsMemset' is true, that means it's
+  /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
+  /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
+  /// does not need to be loaded.  It returns EVT::Other if the type should be
+  /// determined using generic target-independent logic.
   virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
                                   unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
                                   bool /*IsMemset*/,
@@ -720,113 +714,102 @@ public:
     return MVT::Other;
   }
 
-  /// isSafeMemOpType - Returns true if it's safe to use load / store of the
-  /// specified type to expand memcpy / memset inline. This is mostly true
-  /// for all types except for some special cases. For example, on X86
-  /// targets without SSE2 f64 load / store are done with fldl / fstpl which
-  /// also does type conversion. Note the specified type doesn't have to be
-  /// legal as the hook is used before type legalization.
+  /// Returns true if it's safe to use load / store of the specified type to
+  /// expand memcpy / memset inline.
+  ///
+  /// This is mostly true for all types except for some special cases. For
+  /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
+  /// fstpl which also does type conversion. Note the specified type doesn't
+  /// have to be legal as the hook is used before type legalization.
   virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
 
-  /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
-  /// to implement llvm.setjmp.
+  /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
   bool usesUnderscoreSetJmp() const {
     return UseUnderscoreSetJmp;
   }
 
-  /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
-  /// to implement llvm.longjmp.
+  /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
   bool usesUnderscoreLongJmp() const {
     return UseUnderscoreLongJmp;
   }
 
-  /// supportJumpTables - return whether the target can generate code for
-  /// jump tables.
+  /// Return whether the target can generate code for jump tables.
   bool supportJumpTables() const {
     return SupportJumpTables;
   }
 
-  /// getMinimumJumpTableEntries - return integer threshold on number of
-  /// blocks to use jump tables rather than if sequence.
+  /// Return integer threshold on number of blocks to use jump tables rather
+  /// than if sequence.
   int getMinimumJumpTableEntries() const {
     return MinimumJumpTableEntries;
   }
 
-  /// getStackPointerRegisterToSaveRestore - If a physical register, this
-  /// specifies the register that llvm.savestack/llvm.restorestack should save
-  /// and restore.
+  /// If a physical register, this specifies the register that
+  /// llvm.savestack/llvm.restorestack should save and restore.
   unsigned getStackPointerRegisterToSaveRestore() const {
     return StackPointerRegisterToSaveRestore;
   }
 
-  /// getExceptionPointerRegister - If a physical register, this returns
-  /// the register that receives the exception address on entry to a landing
-  /// pad.
+  /// If a physical register, this returns the register that receives the
+  /// exception address on entry to a landing pad.
   unsigned getExceptionPointerRegister() const {
     return ExceptionPointerRegister;
   }
 
-  /// getExceptionSelectorRegister - If a physical register, this returns
-  /// the register that receives the exception typeid on entry to a landing
-  /// pad.
+  /// If a physical register, this returns the register that receives the
+  /// exception typeid on entry to a landing pad.
   unsigned getExceptionSelectorRegister() const {
     return ExceptionSelectorRegister;
   }
 
-  /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
-  /// set, the default is 200)
+  /// Returns the target's jmp_buf size in bytes (if never set, the default is
+  /// 200)
   unsigned getJumpBufSize() const {
     return JumpBufSize;
   }
 
-  /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
-  /// (if never set, the default is 0)
+  /// Returns the target's jmp_buf alignment in bytes (if never set, the default
+  /// is 0)
   unsigned getJumpBufAlignment() const {
     return JumpBufAlignment;
   }
 
-  /// getMinStackArgumentAlignment - return the minimum stack alignment of an
-  /// argument.
+  /// Return the minimum stack alignment of an argument.
   unsigned getMinStackArgumentAlignment() const {
     return MinStackArgumentAlignment;
   }
 
-  /// getMinFunctionAlignment - return the minimum function alignment.
-  ///
+  /// Return the minimum function alignment.
   unsigned getMinFunctionAlignment() const {
     return MinFunctionAlignment;
   }
 
-  /// getPrefFunctionAlignment - return the preferred function alignment.
-  ///
+  /// Return the preferred function alignment.
   unsigned getPrefFunctionAlignment() const {
     return PrefFunctionAlignment;
   }
 
-  /// getPrefLoopAlignment - return the preferred loop alignment.
-  ///
+  /// Return the preferred loop alignment.
   unsigned getPrefLoopAlignment() const {
     return PrefLoopAlignment;
   }
 
-  /// getInsertFencesFor - return whether the DAG builder should automatically
-  /// insert fences and reduce ordering for atomics.
-  ///
+  /// Return whether the DAG builder should automatically insert fences and
+  /// reduce ordering for atomics.
   bool getInsertFencesForAtomic() const {
     return InsertFencesForAtomic;
   }
 
-  /// getStackCookieLocation - Return true if the target stores stack
-  /// protector cookies at a fixed offset in some non-standard address
-  /// space, and populates the address space and offset as
-  /// appropriate.
+  /// Return true if the target stores stack protector cookies at a fixed offset
+  /// in some non-standard address space, and populates the address space and
+  /// offset as appropriate.
   virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
                                       unsigned &/*Offset*/) const {
     return false;
   }
 
-  /// getMaximalGlobalOffset - Returns the maximal possible offset which can be
-  /// used for loads / stores from the global.
+  /// Returns the maximal possible offset which can be used for loads / stores
+  /// from the global.
   virtual unsigned getMaximalGlobalOffset() const {
     return 0;
   }
@@ -852,106 +835,98 @@ public:
   virtual void resetOperationActions() {}
 
 protected:
-  /// setBooleanContents - Specify how the target extends the result of a
-  /// boolean value from i1 to a wider type.  See getBooleanContents.
+  /// Specify how the target extends the result of a boolean value from i1 to a
+  /// wider type.  See getBooleanContents.
   void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
-  /// setBooleanVectorContents - Specify how the target extends the result
-  /// of a vector boolean value from a vector of i1 to a wider type.  See
-  /// getBooleanContents.
+
+  /// Specify how the target extends the result of a vector boolean value from a
+  /// vector of i1 to a wider type.  See getBooleanContents.
   void setBooleanVectorContents(BooleanContent Ty) {
     BooleanVectorContents = Ty;
   }
 
-  /// setSchedulingPreference - Specify the target scheduling preference.
+  /// Specify the target scheduling preference.
   void setSchedulingPreference(Sched::Preference Pref) {
     SchedPreferenceInfo = Pref;
   }
 
-  /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
-  /// use _setjmp to implement llvm.setjmp or the non _ version.
-  /// Defaults to false.
+  /// Indicate whether this target prefers to use _setjmp to implement
+  /// llvm.setjmp or the non _ version.  Defaults to false.
   void setUseUnderscoreSetJmp(bool Val) {
     UseUnderscoreSetJmp = Val;
   }
 
-  /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
-  /// use _longjmp to implement llvm.longjmp or the non _ version.
-  /// Defaults to false.
+  /// Indicate whether this target prefers to use _longjmp to implement
+  /// llvm.longjmp or the non _ version.  Defaults to false.
   void setUseUnderscoreLongJmp(bool Val) {
     UseUnderscoreLongJmp = Val;
   }
 
-  /// setSupportJumpTables - Indicate whether the target can generate code for
-  /// jump tables.
+  /// Indicate whether the target can generate code for jump tables.
   void setSupportJumpTables(bool Val) {
     SupportJumpTables = Val;
   }
 
-  /// setMinimumJumpTableEntries - Indicate the number of blocks to generate
-  /// jump tables rather than if sequence.
+  /// Indicate the number of blocks to generate jump tables rather than if
+  /// sequence.
   void setMinimumJumpTableEntries(int Val) {
     MinimumJumpTableEntries = Val;
   }
 
-  /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
-  /// specifies the register that llvm.savestack/llvm.restorestack should save
-  /// and restore.
+  /// If set to a physical register, this specifies the register that
+  /// llvm.savestack/llvm.restorestack should save and restore.
   void setStackPointerRegisterToSaveRestore(unsigned R) {
     StackPointerRegisterToSaveRestore = R;
   }
 
-  /// setExceptionPointerRegister - If set to a physical register, this sets
-  /// the register that receives the exception address on entry to a landing
-  /// pad.
+  /// If set to a physical register, this sets the register that receives the
+  /// exception address on entry to a landing pad.
   void setExceptionPointerRegister(unsigned R) {
     ExceptionPointerRegister = R;
   }
 
-  /// setExceptionSelectorRegister - If set to a physical register, this sets
-  /// the register that receives the exception typeid on entry to a landing
-  /// pad.
+  /// If set to a physical register, this sets the register that receives the
+  /// exception typeid on entry to a landing pad.
   void setExceptionSelectorRegister(unsigned R) {
     ExceptionSelectorRegister = R;
   }
 
-  /// SelectIsExpensive - Tells the code generator not to expand operations
-  /// into sequences that use the select operations if possible.
+  /// Tells the code generator not to expand operations into sequences that use
+  /// the select operations if possible.
   void setSelectIsExpensive(bool isExpensive = true) {
     SelectIsExpensive = isExpensive;
   }
 
-  /// JumpIsExpensive - Tells the code generator not to expand sequence of
-  /// operations into a separate sequences that increases the amount of
-  /// flow control.
+  /// Tells the code generator not to expand sequence of operations into a
+  /// separate sequences that increases the amount of flow control.
   void setJumpIsExpensive(bool isExpensive = true) {
     JumpIsExpensive = isExpensive;
   }
 
-  /// setIntDivIsCheap - Tells the code generator that integer divide is
-  /// expensive, and if possible, should be replaced by an alternate sequence
-  /// of instructions not containing an integer divide.
+  /// Tells the code generator that integer divide is expensive, and if
+  /// possible, should be replaced by an alternate sequence of instructions not
+  /// containing an integer divide.
   void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
 
-  /// addBypassSlowDiv - Tells the code generator which bitwidths to bypass.
+  /// Tells the code generator which bitwidths to bypass.
   void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
     BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
   }
 
-  /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
-  /// srl/add/sra for a signed divide by power of two, and let the target handle
-  /// it.
+  /// Tells the code generator that it shouldn't generate srl/add/sra for a
+  /// signed divide by power of two, and let the target handle it.
   void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
 
-  /// addRegisterClass - Add the specified register class as an available
-  /// regclass for the specified value type.  This indicates the selector can
-  /// handle values of that class natively.
+  /// Add the specified register class as an available regclass for the
+  /// specified value type. This indicates the selector can handle values of
+  /// that class natively.
   void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
     assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
     AvailableRegClasses.push_back(std::make_pair(VT, RC));
     RegClassForVT[VT.SimpleTy] = RC;
   }
 
-  /// clearRegisterClasses - Remove all register classes.
+  /// Remove all register classes.
   void clearRegisterClasses() {
     memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
 
@@ -962,25 +937,25 @@ protected:
   void clearOperationActions() {
   }
 
-  /// findRepresentativeClass - Return the largest legal super-reg register class
-  /// of the register class for the specified type and its associated "cost".
+  /// Return the largest legal super-reg register class of the register class
+  /// for the specified type and its associated "cost".
   virtual std::pair<const TargetRegisterClass*, uint8_t>
   findRepresentativeClass(MVT VT) const;
 
-  /// computeRegisterProperties - Once all of the register classes are added,
-  /// this allows us to compute derived properties we expose.
+  /// Once all of the register classes are added, this allows us to compute
+  /// derived properties we expose.
   void computeRegisterProperties();
 
-  /// setOperationAction - Indicate that the specified operation does not work
-  /// with the specified type and indicate what to do about it.
+  /// Indicate that the specified operation does not work with the specified
+  /// type and indicate what to do about it.
   void setOperationAction(unsigned Op, MVT VT,
                           LegalizeAction Action) {
     assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
     OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
   }
 
-  /// setLoadExtAction - Indicate that the specified load with extension does
-  /// not work with the specified type and indicate what to do about it.
+  /// Indicate that the specified load with extension does not work with the
+  /// specified type and indicate what to do about it.
   void setLoadExtAction(unsigned ExtType, MVT VT,
                         LegalizeAction Action) {
     assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
@@ -988,8 +963,8 @@ protected:
     LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
   }
 
-  /// setTruncStoreAction - Indicate that the specified truncating store does
-  /// not work with the specified type and indicate what to do about it.
+  /// Indicate that the specified truncating store does not work with the
+  /// specified type and indicate what to do about it.
   void setTruncStoreAction(MVT ValVT, MVT MemVT,
                            LegalizeAction Action) {
     assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
@@ -997,9 +972,10 @@ protected:
     TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
   }
 
-  /// setIndexedLoadAction - Indicate that the specified indexed load does or
-  /// does not work with the specified type and indicate what to do abort
-  /// it. NOTE: All indexed mode loads are initialized to Expand in
+  /// Indicate that the specified indexed load does or does not work with the
+  /// specified type and indicate what to do abort it.
+  ///
+  /// NOTE: All indexed mode loads are initialized to Expand in
   /// TargetLowering.cpp
   void setIndexedLoadAction(unsigned IdxMode, MVT VT,
                             LegalizeAction Action) {
@@ -1010,9 +986,10 @@ protected:
     IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
   }
 
-  /// setIndexedStoreAction - Indicate that the specified indexed store does or
-  /// does not work with the specified type and indicate what to do about
-  /// it. NOTE: All indexed mode stores are initialized to Expand in
+  /// Indicate that the specified indexed store does or does not work with the
+  /// specified type and indicate what to do about it.
+  ///
+  /// NOTE: All indexed mode stores are initialized to Expand in
   /// TargetLowering.cpp
   void setIndexedStoreAction(unsigned IdxMode, MVT VT,
                              LegalizeAction Action) {
@@ -1023,8 +1000,8 @@ protected:
     IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
   }
 
-  /// setCondCodeAction - Indicate that the specified condition code is or isn't
-  /// supported on the target and indicate what to do about it.
+  /// Indicate that the specified condition code is or isn't supported on the
+  /// target and indicate what to do about it.
   void setCondCodeAction(ISD::CondCode CC, MVT VT,
                          LegalizeAction Action) {
     assert(VT < MVT::LAST_VALUETYPE &&
@@ -1039,63 +1016,59 @@ protected:
       |= (uint64_t)Action << (VT.SimpleTy & 0x1F)*2;
   }
 
-  /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
-  /// promotion code defaults to trying a larger integer/fp until it can find
-  /// one that works.  If that default is insufficient, this method can be used
-  /// by the target to override the default.
+  /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
+  /// to trying a larger integer/fp until it can find one that works. If that
+  /// default is insufficient, this method can be used by the target to override
+  /// the default.
   void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
     PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
   }
 
-  /// setTargetDAGCombine - Targets should invoke this method for each target
-  /// independent node that they want to provide a custom DAG combiner for by
-  /// implementing the PerformDAGCombine virtual method.
+  /// Targets should invoke this method for each target independent node that
+  /// they want to provide a custom DAG combiner for by implementing the
+  /// PerformDAGCombine virtual method.
   void setTargetDAGCombine(ISD::NodeType NT) {
     assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
     TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
   }
 
-  /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
-  /// bytes); default is 200
+  /// Set the target's required jmp_buf buffer size (in bytes); default is 200
   void setJumpBufSize(unsigned Size) {
     JumpBufSize = Size;
   }
 
-  /// setJumpBufAlignment - Set the target's required jmp_buf buffer
-  /// alignment (in bytes); default is 0
+  /// Set the target's required jmp_buf buffer alignment (in bytes); default is
+  /// 0
   void setJumpBufAlignment(unsigned Align) {
     JumpBufAlignment = Align;
   }
 
-  /// setMinFunctionAlignment - Set the target's minimum function alignment (in
-  /// log2(bytes))
+  /// Set the target's minimum function alignment (in log2(bytes))
   void setMinFunctionAlignment(unsigned Align) {
     MinFunctionAlignment = Align;
   }
 
-  /// setPrefFunctionAlignment - Set the target's preferred function alignment.
-  /// This should be set if there is a performance benefit to
-  /// higher-than-minimum alignment (in log2(bytes))
+  /// Set the target's preferred function alignment.  This should be set if
+  /// there is a performance benefit to higher-than-minimum alignment (in
+  /// log2(bytes))
   void setPrefFunctionAlignment(unsigned Align) {
     PrefFunctionAlignment = Align;
   }
 
-  /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
-  /// alignment is zero, it means the target does not care about loop alignment.
-  /// The alignment is specified in log2(bytes).
+  /// Set the target's preferred loop alignment. Default alignment is zero, it
+  /// means the target does not care about loop alignment.  The alignment is
+  /// specified in log2(bytes).
   void setPrefLoopAlignment(unsigned Align) {
     PrefLoopAlignment = Align;
   }
 
-  /// setMinStackArgumentAlignment - Set the minimum stack alignment of an
-  /// argument (in log2(bytes)).
+  /// Set the minimum stack alignment of an argument (in log2(bytes)).
   void setMinStackArgumentAlignment(unsigned Align) {
     MinStackArgumentAlignment = Align;
   }
 
-  /// setInsertFencesForAtomic - Set if the DAG builder should
-  /// automatically insert fences and reduce the order of atomic memory
-  /// operations to Monotonic.
+  /// Set if the DAG builder should automatically insert fences and reduce the
+  /// order of atomic memory operations to Monotonic.
   void setInsertFencesForAtomic(bool fence) {
     InsertFencesForAtomic = fence;
   }
@@ -1105,25 +1078,24 @@ public:
   // Addressing mode description hooks (used by LSR etc).
   //
 
-  /// GetAddrModeArguments - CodeGenPrepare sinks address calculations into the
-  /// same BB as Load/Store instructions reading the address.  This allows as
-  /// much computation as possible to be done in the address mode for that
-  /// operand.  This hook lets targets also pass back when this should be done
-  /// on intrinsics which load/store.
+  /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
+  /// instructions reading the address. This allows as much computation as
+  /// possible to be done in the address mode for that operand. This hook lets
+  /// targets also pass back when this should be done on intrinsics which
+  /// load/store.
   virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
                                     SmallVectorImpl<Value*> &/*Ops*/,
                                     Type *&/*AccessTy*/) const {
     return false;
   }
 
-  /// AddrMode - This represents an addressing mode of:
+  /// This represents an addressing mode of:
   ///    BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
   /// If BaseGV is null,  there is no BaseGV.
   /// If BaseOffs is zero, there is no base offset.
   /// If HasBaseReg is false, there is no base register.
   /// If Scale is zero, there is no ScaleReg.  Scale of 1 indicates a reg with
   /// no scale.
-  ///
   struct AddrMode {
     GlobalValue *BaseGV;
     int64_t      BaseOffs;
@@ -1132,16 +1104,17 @@ public:
     AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
   };
 
-  /// isLegalAddressingMode - Return true if the addressing mode represented by
-  /// AM is legal for this target, for a load/store of the specified type.
+  /// Return true if the addressing mode represented by AM is legal for this
+  /// target, for a load/store of the specified type.
+  ///
   /// The type may be VoidTy, in which case only return true if the addressing
-  /// mode is legal for a load/store of any legal type.
-  /// TODO: Handle pre/postinc as well.
+  /// mode is legal for a load/store of any legal type.  TODO: Handle
+  /// pre/postinc as well.
   virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
 
-  /// \brief Return the cost of the scaling factor used in the addressing
-  /// mode represented by AM for this target, for a load/store
-  /// of the specified type.
+  /// \brief Return the cost of the scaling factor used in the addressing mode
+  /// represented by AM for this target, for a load/store of the specified type.
+  ///
   /// If the AM is supported, the return value must be >= 0.
   /// If the AM is not supported, it returns a negative value.
   /// TODO: Handle pre/postinc as well.
@@ -1151,25 +1124,23 @@ public:
     return -1;
   }
 
-  /// isLegalICmpImmediate - Return true if the specified immediate is legal
-  /// icmp immediate, that is the target has icmp instructions which can compare
-  /// a register against the immediate without having to materialize the
-  /// immediate into a register.
+  /// Return true if the specified immediate is legal icmp immediate, that is
+  /// the target has icmp instructions which can compare a register against the
+  /// immediate without having to materialize the immediate into a register.
   virtual bool isLegalICmpImmediate(int64_t) const {
     return true;
   }
 
-  /// isLegalAddImmediate - Return true if the specified immediate is legal
-  /// add immediate, that is the target has add instructions which can add
-  /// a register with the immediate without having to materialize the
-  /// immediate into a register.
+  /// Return true if the specified immediate is legal add immediate, that is the
+  /// target has add instructions which can add a register with the immediate
+  /// without having to materialize the immediate into a register.
   virtual bool isLegalAddImmediate(int64_t) const {
     return true;
   }
 
-  /// isTruncateFree - Return true if it's free to truncate a value of
-  /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
-  /// register EAX to i16 by referencing its sub-register AX.
+  /// Return true if it's free to truncate a value of type Ty1 to type
+  /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
+  /// by referencing its sub-register AX.
   virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
     return false;
   }
@@ -1178,14 +1149,14 @@ public:
     return false;
   }
 
-  /// isZExtFree - Return true if any actual instruction that defines a
-  /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
-  /// register. This does not necessarily include registers defined in
-  /// unknown ways, such as incoming arguments, or copies from unknown
-  /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
-  /// does not necessarily apply to truncate instructions. e.g. on x86-64,
-  /// all instructions that define 32-bit values implicit zero-extend the
-  /// result out to 64 bits.
+  /// Return true if any actual instruction that defines a value of type Ty1
+  /// implicitly zero-extends the value to Ty2 in the result register.
+  ///
+  /// This does not necessarily include registers defined in unknown ways, such
+  /// as incoming arguments, or copies from unknown virtual registers. Also, if
+  /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
+  /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
+  /// values implicit zero-extend the result out to 64 bits.
   virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
     return false;
   }
@@ -1194,29 +1165,28 @@ public:
     return false;
   }
 
-  /// isZExtFree - Return true if zero-extending the specific node Val to type
-  /// VT2 is free (either because it's implicitly zero-extended such as ARM
-  /// ldrb / ldrh or because it's folded such as X86 zero-extending loads).
+  /// Return true if zero-extending the specific node Val to type VT2 is free
+  /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
+  /// because it's folded such as X86 zero-extending loads).
   virtual bool isZExtFree(SDValue Val, EVT VT2) const {
     return isZExtFree(Val.getValueType(), VT2);
   }
 
-  /// isFNegFree - Return true if an fneg operation is free to the point where
-  /// it is never worthwhile to replace it with a bitwise operation.
+  /// Return true if an fneg operation is free to the point where it is never
+  /// worthwhile to replace it with a bitwise operation.
   virtual bool isFNegFree(EVT) const {
     return false;
   }
 
-  /// isFAbsFree - Return true if an fneg operation is free to the point where
-  /// it is never worthwhile to replace it with a bitwise operation.
+  /// Return true if an fneg operation is free to the point where it is never
+  /// worthwhile to replace it with a bitwise operation.
   virtual bool isFAbsFree(EVT) const {
     return false;
   }
 
-  /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
-  /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
-  /// expanded to FMAs when this method returns true, otherwise fmuladd is
-  /// expanded to fmul + fadd.
+  /// Return true if an FMA operation is faster than a pair of fmul and fadd
+  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
+  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
   ///
   /// NOTE: This may be called before legalization on types for which FMAs are
   /// not legal, but should return true if those types will eventually legalize
@@ -1226,9 +1196,9 @@ public:
     return false;
   }
 
-  /// isNarrowingProfitable - Return true if it's profitable to narrow
-  /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
-  /// from i32 to i8 but not from i32 to i16.
+  /// Return true if it's profitable to narrow operations of type VT1 to
+  /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
+  /// i32 to i16.
   virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
     return false;
   }
@@ -1237,38 +1207,34 @@ public:
   // Runtime Library hooks
   //
 
-  /// setLibcallName - Rename the default libcall routine name for the specified
-  /// libcall.
+  /// Rename the default libcall routine name for the specified libcall.
   void setLibcallName(RTLIB::Libcall Call, const char *Name) {
     LibcallRoutineNames[Call] = Name;
   }
 
-  /// getLibcallName - Get the libcall routine name for the specified libcall.
-  ///
+  /// Get the libcall routine name for the specified libcall.
   const char *getLibcallName(RTLIB::Libcall Call) const {
     return LibcallRoutineNames[Call];
   }
 
-  /// setCmpLibcallCC - Override the default CondCode to be used to test the
-  /// result of the comparison libcall against zero.
+  /// Override the default CondCode to be used to test the result of the
+  /// comparison libcall against zero.
   void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
     CmpLibcallCCs[Call] = CC;
   }
 
-  /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
-  /// the comparison libcall against zero.
+  /// Get the CondCode that's to be used to test the result of the comparison
+  /// libcall against zero.
   ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
     return CmpLibcallCCs[Call];
   }
 
-  /// setLibcallCallingConv - Set the CallingConv that should be used for the
-  /// specified libcall.
+  /// Set the CallingConv that should be used for the specified libcall.
   void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
     LibcallCallingConvs[Call] = CC;
   }
 
-  /// getLibcallCallingConv - Get the CallingConv that should be used for the
-  /// specified libcall.
+  /// Get the CallingConv that should be used for the specified libcall.
   CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
     return LibcallCallingConvs[Call];
   }
@@ -1278,171 +1244,160 @@ private:
   const DataLayout *TD;
   const TargetLoweringObjectFile &TLOF;
 
-  /// PointerTy - The type to use for pointers for the default address space,
-  /// usually i32 or i64.
-  ///
+  /// The type to use for pointers for the default address space, usually i32 or
+  /// i64.
   MVT PointerTy;
 
-  /// IsLittleEndian - True if this is a little endian target.
-  ///
+  /// True if this is a little endian target.
   bool IsLittleEndian;
 
-  /// SelectIsExpensive - Tells the code generator not to expand operations
-  /// into sequences that use the select operations if possible.
+  /// Tells the code generator not to expand operations into sequences that use
+  /// the select operations if possible.
   bool SelectIsExpensive;
 
-  /// IntDivIsCheap - Tells the code generator not to expand integer divides by
-  /// constants into a sequence of muls, adds, and shifts.  This is a hack until
-  /// a real cost model is in place.  If we ever optimize for size, this will be
-  /// set to true unconditionally.
+  /// Tells the code generator not to expand integer divides by constants into a
+  /// sequence of muls, adds, and shifts.  This is a hack until a real cost
+  /// model is in place.  If we ever optimize for size, this will be set to true
+  /// unconditionally.
   bool IntDivIsCheap;
 
-  /// BypassSlowDivMap - Tells the code generator to bypass slow divide or
-  /// remainder instructions. For example, BypassSlowDivWidths[32,8] tells the
-  /// code generator to bypass 32-bit integer div/rem with an 8-bit unsigned
-  /// integer div/rem when the operands are positive and less than 256.
+  /// Tells the code generator to bypass slow divide or remainder
+  /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
+  /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
+  /// div/rem when the operands are positive and less than 256.
   DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
 
-  /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
-  /// srl/add/sra for a signed divide by power of two, and let the target handle
-  /// it.
+  /// Tells the code generator that it shouldn't generate srl/add/sra for a
+  /// signed divide by power of two, and let the target handle it.
   bool Pow2DivIsCheap;
 
-  /// JumpIsExpensive - Tells the code generator that it shouldn't generate
-  /// extra flow control instructions and should attempt to combine flow
-  /// control instructions via predication.
+  /// Tells the code generator that it shouldn't generate extra flow control
+  /// instructions and should attempt to combine flow control instructions via
+  /// predication.
   bool JumpIsExpensive;
 
-  /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
-  /// llvm.setjmp.  Defaults to false.
+  /// This target prefers to use _setjmp to implement llvm.setjmp.
+  ///
+  /// Defaults to false.
   bool UseUnderscoreSetJmp;
 
-  /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
-  /// llvm.longjmp.  Defaults to false.
+  /// This target prefers to use _longjmp to implement llvm.longjmp.
+  ///
+  /// Defaults to false.
   bool UseUnderscoreLongJmp;
 
-  /// SupportJumpTables - Whether the target can generate code for jumptables.
-  /// If it's not true, then each jumptable must be lowered into if-then-else's.
+  /// Whether the target can generate code for jumptables.  If it's not true,
+  /// then each jumptable must be lowered into if-then-else's.
   bool SupportJumpTables;
 
-  /// MinimumJumpTableEntries - Number of blocks threshold to use jump tables.
+  /// Number of blocks threshold to use jump tables.
   int MinimumJumpTableEntries;
 
-  /// BooleanContents - Information about the contents of the high-bits in
-  /// boolean values held in a type wider than i1.  See getBooleanContents.
+  /// Information about the contents of the high-bits in boolean values held in
+  /// a type wider than i1. See getBooleanContents.
   BooleanContent BooleanContents;
-  /// BooleanVectorContents - Information about the contents of the high-bits
-  /// in boolean vector values when the element type is wider than i1.  See
-  /// getBooleanContents.
+
+  /// Information about the contents of the high-bits in boolean vector values
+  /// when the element type is wider than i1. See getBooleanContents.
   BooleanContent BooleanVectorContents;
 
-  /// SchedPreferenceInfo - The target scheduling preference: shortest possible
-  /// total cycles or lowest register usage.
+  /// The target scheduling preference: shortest possible total cycles or lowest
+  /// register usage.
   Sched::Preference SchedPreferenceInfo;
 
-  /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
+  /// The size, in bytes, of the target's jmp_buf buffers
   unsigned JumpBufSize;
 
-  /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
-  /// buffers
+  /// The alignment, in bytes, of the target's jmp_buf buffers
   unsigned JumpBufAlignment;
 
-  /// MinStackArgumentAlignment - The minimum alignment that any argument
-  /// on the stack needs to have.
-  ///
+  /// The minimum alignment that any argument on the stack needs to have.
   unsigned MinStackArgumentAlignment;
 
-  /// MinFunctionAlignment - The minimum function alignment (used when
-  /// optimizing for size, and to prevent explicitly provided alignment
-  /// from leading to incorrect code).
-  ///
+  /// The minimum function alignment (used when optimizing for size, and to
+  /// prevent explicitly provided alignment from leading to incorrect code).
   unsigned MinFunctionAlignment;
 
-  /// PrefFunctionAlignment - The preferred function alignment (used when
-  /// alignment unspecified and optimizing for speed).
-  ///
+  /// The preferred function alignment (used when alignment unspecified and
+  /// optimizing for speed).
   unsigned PrefFunctionAlignment;
 
-  /// PrefLoopAlignment - The preferred loop alignment.
-  ///
+  /// The preferred loop alignment.
   unsigned PrefLoopAlignment;
 
-  /// InsertFencesForAtomic - Whether the DAG builder should automatically
-  /// insert fences and reduce ordering for atomics.  (This will be set for
-  /// for most architectures with weak memory ordering.)
+  /// Whether the DAG builder should automatically insert fences and reduce
+  /// ordering for atomics.  (This will be set for for most architectures with
+  /// weak memory ordering.)
   bool InsertFencesForAtomic;
 
-  /// StackPointerRegisterToSaveRestore - If set to a physical register, this
-  /// specifies the register that llvm.savestack/llvm.restorestack should save
-  /// and restore.
+  /// If set to a physical register, this specifies the register that
+  /// llvm.savestack/llvm.restorestack should save and restore.
   unsigned StackPointerRegisterToSaveRestore;
 
-  /// ExceptionPointerRegister - If set to a physical register, this specifies
-  /// the register that receives the exception address on entry to a landing
-  /// pad.
+  /// If set to a physical register, this specifies the register that receives
+  /// the exception address on entry to a landing pad.
   unsigned ExceptionPointerRegister;
 
-  /// ExceptionSelectorRegister - If set to a physical register, this specifies
-  /// the register that receives the exception typeid on entry to a landing
-  /// pad.
+  /// If set to a physical register, this specifies the register that receives
+  /// the exception typeid on entry to a landing pad.
   unsigned ExceptionSelectorRegister;
 
-  /// RegClassForVT - This indicates the default register class to use for
-  /// each ValueType the target supports natively.
+  /// This indicates the default register class to use for each ValueType the
+  /// target supports natively.
   const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
   unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
   MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
 
-  /// RepRegClassForVT - This indicates the "representative" register class to
-  /// use for each ValueType the target supports natively. This information is
-  /// used by the scheduler to track register pressure. By default, the
-  /// representative register class is the largest legal super-reg register
-  /// class of the register class of the specified type. e.g. On x86, i8, i16,
-  /// and i32's representative class would be GR32.
+  /// This indicates the "representative" register class to use for each
+  /// ValueType the target supports natively. This information is used by the
+  /// scheduler to track register pressure. By default, the representative
+  /// register class is the largest legal super-reg register class of the
+  /// register class of the specified type. e.g. On x86, i8, i16, and i32's
+  /// representative class would be GR32.
   const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
 
-  /// RepRegClassCostForVT - This indicates the "cost" of the "representative"
-  /// register class for each ValueType. The cost is used by the scheduler to
-  /// approximate register pressure.
+  /// This indicates the "cost" of the "representative" register class for each
+  /// ValueType. The cost is used by the scheduler to approximate register
+  /// pressure.
   uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
 
-  /// TransformToType - For any value types we are promoting or expanding, this
-  /// contains the value type that we are changing to.  For Expanded types, this
-  /// contains one step of the expand (e.g. i64 -> i32), even if there are
-  /// multiple steps required (e.g. i64 -> i16).  For types natively supported
-  /// by the system, this holds the same type (e.g. i32 -> i32).
+  /// For any value types we are promoting or expanding, this contains the value
+  /// type that we are changing to.  For Expanded types, this contains one step
+  /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
+  /// (e.g. i64 -> i16).  For types natively supported by the system, this holds
+  /// the same type (e.g. i32 -> i32).
   MVT TransformToType[MVT::LAST_VALUETYPE];
 
-  /// OpActions - For each operation and each value type, keep a LegalizeAction
-  /// that indicates how instruction selection should deal with the operation.
-  /// Most operations are Legal (aka, supported natively by the target), but
+  /// For each operation and each value type, keep a LegalizeAction that
+  /// indicates how instruction selection should deal with the operation.  Most
+  /// operations are Legal (aka, supported natively by the target), but
   /// operations that are not should be described.  Note that operations on
   /// non-legal value types are not described here.
   uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
 
-  /// LoadExtActions - For each load extension type and each value type,
-  /// keep a LegalizeAction that indicates how instruction selection should deal
-  /// with a load of a specific value type and extension type.
+  /// For each load extension type and each value type, keep a LegalizeAction
+  /// that indicates how instruction selection should deal with a load of a
+  /// specific value type and extension type.
   uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
 
-  /// TruncStoreActions - For each value type pair keep a LegalizeAction that
-  /// indicates whether a truncating store of a specific value type and
-  /// truncating type is legal.
+  /// For each value type pair keep a LegalizeAction that indicates whether a
+  /// truncating store of a specific value type and truncating type is legal.
   uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
 
-  /// IndexedModeActions - For each indexed mode and each value type,
-  /// keep a pair of LegalizeAction that indicates how instruction
-  /// selection should deal with the load / store.  The first dimension is the
-  /// value_type for the reference. The second dimension represents the various
-  /// modes for load store.
+  /// For each indexed mode and each value type, keep a pair of LegalizeAction
+  /// that indicates how instruction selection should deal with the load /
+  /// store.
+  ///
+  /// The first dimension is the value_type for the reference. The second
+  /// dimension represents the various modes for load store.
   uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
 
-  /// CondCodeActions - For each condition code (ISD::CondCode) keep a
-  /// LegalizeAction that indicates how instruction selection should
-  /// deal with the condition code.
-  /// Because each CC action takes up 2 bits, we need to have the array size
-  /// be large enough to fit all of the value types. This can be done by
-  /// dividing the MVT::LAST_VALUETYPE by 32 and adding one.
+  /// For each condition code (ISD::CondCode) keep a LegalizeAction that
+  /// indicates how instruction selection should deal with the condition code.
+  ///
+  /// Because each CC action takes up 2 bits, we need to have the array size be
+  /// large enough to fit all of the value types. This can be done by dividing
+  /// the MVT::LAST_VALUETYPE by 32 and adding one.
   uint64_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE / 32) + 1];
 
   ValueTypeActionImpl ValueTypeActions;
@@ -1578,34 +1533,34 @@ public:
 private:
   std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
 
-  /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
-  /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
-  /// which sets a bit in this array.
+  /// Targets can specify ISD nodes that they would like PerformDAGCombine
+  /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
+  /// array.
   unsigned char
   TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
 
-  /// PromoteToType - For operations that must be promoted to a specific type,
-  /// this holds the destination type.  This map should be sparse, so don't hold
-  /// it as an array.
+  /// For operations that must be promoted to a specific type, this holds the
+  /// destination type.  This map should be sparse, so don't hold it as an
+  /// array.
   ///
   /// Targets add entries to this map with AddPromotedToType(..), clients access
   /// this with getTypeToPromoteTo(..).
   std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
     PromoteToType;
 
-  /// LibcallRoutineNames - Stores the name each libcall.
-  ///
+  /// Stores the name each libcall.
   const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
 
-  /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
-  /// of each of the comparison libcall against zero.
+  /// The ISD::CondCode that should be used to test the result of each of the
+  /// comparison libcall against zero.
   ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
 
-  /// LibcallCallingConvs - Stores the CallingConv that should be used for each
-  /// libcall.
+  /// Stores the CallingConv that should be used for each libcall.
   CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
 
 protected:
+  /// \brief Specify maximum number of store instructions per memset call.
+  ///
   /// When lowering \@llvm.memset this field specifies the maximum number of
   /// store operations that may be substituted for the call to memset. Targets
   /// must set this value based on the cost threshold for that target. Targets
@@ -1614,13 +1569,14 @@ protected:
   /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
   /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
   /// store.  This only applies to setting a constant array of a constant size.
-  /// @brief Specify maximum number of store instructions per memset call.
   unsigned MaxStoresPerMemset;
 
   /// Maximum number of stores operations that may be substituted for the call
   /// to memset, used for functions with OptSize attribute.
   unsigned MaxStoresPerMemsetOptSize;
 
+  /// \brief Specify maximum bytes of store instructions per memcpy call.
+  ///
   /// When lowering \@llvm.memcpy this field specifies the maximum number of
   /// store operations that may be substituted for a call to memcpy. Targets
   /// must set this value based on the cost threshold for that target. Targets
@@ -1630,13 +1586,14 @@ protected:
   /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
   /// and one 1-byte store. This only applies to copying a constant array of
   /// constant size.
-  /// @brief Specify maximum bytes of store instructions per memcpy call.
   unsigned MaxStoresPerMemcpy;
 
-  /// Maximum number of store operations that may be substituted for a call
-  /// to memcpy, used for functions with OptSize attribute.
+  /// Maximum number of store operations that may be substituted for a call to
+  /// memcpy, used for functions with OptSize attribute.
   unsigned MaxStoresPerMemcpyOptSize;
 
+  /// \brief Specify maximum bytes of store instructions per memmove call.
+  ///
   /// When lowering \@llvm.memmove this field specifies the maximum number of
   /// store instructions that may be substituted for a call to memmove. Targets
   /// must set this value based on the cost threshold for that target. Targets
@@ -1645,31 +1602,27 @@ protected:
   /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
   /// with 8-bit alignment would result in nine 1-byte stores.  This only
   /// applies to copying a constant array of constant size.
-  /// @brief Specify maximum bytes of store instructions per memmove call.
   unsigned MaxStoresPerMemmove;
 
-  /// Maximum number of store instructions that may be substituted for a call
-  /// to memmove, used for functions with OpSize attribute.
+  /// Maximum number of store instructions that may be substituted for a call to
+  /// memmove, used for functions with OpSize attribute.
   unsigned MaxStoresPerMemmoveOptSize;
 
-  /// PredictableSelectIsExpensive - Tells the code generator that select is
-  /// more expensive than a branch if the branch is usually predicted right.
+  /// Tells the code generator that select is more expensive than a branch if
+  /// the branch is usually predicted right.
   bool PredictableSelectIsExpensive;
 
 protected:
-  /// isLegalRC - Return true if the value types that can be represented by the
-  /// specified register class are all legal.
+  /// Return true if the value types that can be represented by the specified
+  /// register class are all legal.
   bool isLegalRC(const TargetRegisterClass *RC) const;
 };
 
-//===----------------------------------------------------------------------===//
-/// TargetLowering - This class defines information used to lower LLVM code to
-/// legal SelectionDAG operators that the target instruction selector can accept
-/// natively.
+/// This class defines information used to lower LLVM code to legal SelectionDAG
+/// operators that the target instruction selector can accept natively.
 ///
 /// This class also defines callbacks that targets must implement to lower
 /// target-specific constructs to SelectionDAG operators.
-///
 class TargetLowering : public TargetLoweringBase {
   TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
   void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
@@ -1679,9 +1632,9 @@ public:
   explicit TargetLowering(const TargetMachine &TM,
                           const TargetLoweringObjectFile *TLOF);
 
-  /// getPreIndexedAddressParts - returns true by value, base pointer and
-  /// offset pointer and addressing mode by reference if the node's address
-  /// can be legally represented as pre-indexed load / store address.
+  /// Returns true by value, base pointer and offset pointer and addressing mode
+  /// by reference if the node's address can be legally represented as
+  /// pre-indexed load / store address.
   virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
                                          SDValue &/*Offset*/,
                                          ISD::MemIndexedMode &/*AM*/,
@@ -1689,9 +1642,9 @@ public:
     return false;
   }
 
-  /// getPostIndexedAddressParts - returns true by value, base pointer and
-  /// offset pointer and addressing mode by reference if this node can be
-  /// combined with a load / store to form a post-indexed load / store.
+  /// Returns true by value, base pointer and offset pointer and addressing mode
+  /// by reference if this node can be combined with a load / store to form a
+  /// post-indexed load / store.
   virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
                                           SDValue &/*Base*/, SDValue &/*Offset*/,
                                           ISD::MemIndexedMode &/*AM*/,
@@ -1699,9 +1652,8 @@ public:
     return false;
   }
 
-  /// getJumpTableEncoding - Return the entry encoding for a jump table in the
-  /// current function.  The returned value is a member of the
-  /// MachineJumpTableInfo::JTEntryKind enum.
+  /// Return the entry encoding for a jump table in the current function.  The
+  /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
   virtual unsigned getJumpTableEncoding() const;
 
   virtual const MCExpr *
@@ -1711,21 +1663,18 @@ public:
     llvm_unreachable("Need to implement this hook if target has custom JTIs");
   }
 
-  /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
-  /// jumptable.
+  /// Returns relocation base for the given PIC jumptable.
   virtual SDValue getPICJumpTableRelocBase(SDValue Table,
                                            SelectionDAG &DAG) const;
 
-  /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
-  /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
-  /// MCExpr.
+  /// This returns the relocation base for the given PIC jumptable, the same as
+  /// getPICJumpTableRelocBase, but as an MCExpr.
   virtual const MCExpr *
   getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
                                unsigned JTI, MCContext &Ctx) const;
 
-  /// isOffsetFoldingLegal - Return true if folding a constant offset
-  /// with the given GlobalAddress is legal.  It is frequently not legal in
-  /// PIC relocation models.
+  /// Return true if folding a constant offset with the given GlobalAddress is
+  /// legal.  It is frequently not legal in PIC relocation models.
   virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
 
   bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
@@ -1743,9 +1692,9 @@ public:
   // TargetLowering Optimization Methods
   //
 
-  /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
-  /// SDValues for returning information from TargetLowering to its clients
-  /// that want to combine
+  /// A convenience struct that encapsulates a DAG, and two SDValues for
+  /// returning information from TargetLowering to its clients that want to
+  /// combine.
   struct TargetLoweringOpt {
     SelectionDAG &DAG;
     bool LegalTys;
@@ -1766,44 +1715,40 @@ public:
       return true;
     }
 
-    /// ShrinkDemandedConstant - Check to see if the specified operand of the
-    /// specified instruction is a constant integer.  If so, check to see if
-    /// there are any bits set in the constant that are not demanded.  If so,
-    /// shrink the constant and return true.
+    /// Check to see if the specified operand of the specified instruction is a
+    /// constant integer.  If so, check to see if there are any bits set in the
+    /// constant that are not demanded.  If so, shrink the constant and return
+    /// true.
     bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
 
-    /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
-    /// casts are free.  This uses isZExtFree and ZERO_EXTEND for the widening
-    /// cast, but it could be generalized for targets with other types of
-    /// implicit widening casts.
+    /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.  This
+    /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
+    /// generalized for targets with other types of implicit widening casts.
     bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
                           SDLoc dl);
   };
 
-  /// SimplifyDemandedBits - Look at Op.  At this point, we know that only the
-  /// DemandedMask bits of the result of Op are ever used downstream.  If we can
-  /// use this information to simplify Op, create a new simplified DAG node and
-  /// return true, returning the original and new nodes in Old and New.
-  /// Otherwise, analyze the expression and return a mask of KnownOne and
-  /// KnownZero bits for the expression (used to simplify the caller).
-  /// The KnownZero/One bits may only be accurate for those bits in the
-  /// DemandedMask.
+  /// Look at Op.  At this point, we know that only the DemandedMask bits of the
+  /// result of Op are ever used downstream.  If we can use this information to
+  /// simplify Op, create a new simplified DAG node and return true, returning
+  /// the original and new nodes in Old and New.  Otherwise, analyze the
+  /// expression and return a mask of KnownOne and KnownZero bits for the
+  /// expression (used to simplify the caller).  The KnownZero/One bits may only
+  /// be accurate for those bits in the DemandedMask.
   bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
                             APInt &KnownZero, APInt &KnownOne,
                             TargetLoweringOpt &TLO, unsigned Depth = 0) const;
 
-  /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
-  /// Mask are known to be either zero or one and return them in the
-  /// KnownZero/KnownOne bitsets.
+  /// Determine which of the bits specified in Mask are known to be either zero
+  /// or one and return them in the KnownZero/KnownOne bitsets.
   virtual void computeMaskedBitsForTargetNode(const SDValue Op,
                                               APInt &KnownZero,
                                               APInt &KnownOne,
                                               const SelectionDAG &DAG,
                                               unsigned Depth = 0) const;
 
-  /// ComputeNumSignBitsForTargetNode - This method can be implemented by
-  /// targets that want to expose additional information about sign bits to the
-  /// DAG Combiner.
+  /// This method can be implemented by targets that want to expose additional
+  /// information about sign bits to the DAG Combiner.
   virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
                                                    unsigned Depth = 0) const;
 
@@ -1835,20 +1780,20 @@ public:
     void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
   };
 
-  /// SimplifySetCC - Try to simplify a setcc built with the specified operands
-  /// and cc. If it is unable to simplify it, return a null SDValue.
+  /// Try to simplify a setcc built with the specified operands and cc. If it is
+  /// unable to simplify it, return a null SDValue.
   SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
                           ISD::CondCode Cond, bool foldBooleans,
                           DAGCombinerInfo &DCI, SDLoc dl) const;
 
-  /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
-  /// node is a GlobalAddress + offset.
+  /// Returns true (and the GlobalValue and the offset) if the node is a
+  /// GlobalAddress + offset.
   virtual bool
   isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
 
-  /// PerformDAGCombine - This method will be invoked for all target nodes and
-  /// for any target-independent nodes that the target has registered with
-  /// invoke it for.
+  /// This method will be invoked for all target nodes and for any
+  /// target-independent nodes that the target has registered with invoke it
+  /// for.
   ///
   /// The semantics are as follows:
   /// Return Value:
@@ -1861,26 +1806,26 @@ public:
   ///
   virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 
-  /// isTypeDesirableForOp - Return true if the target has native support for
-  /// the specified value type and it is 'desirable' to use the type for the
-  /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
-  /// instruction encodings are longer and some i16 instructions are slow.
+  /// Return true if the target has native support for the specified value type
+  /// and it is 'desirable' to use the type for the given node type. e.g. On x86
+  /// i16 is legal, but undesirable since i16 instruction encodings are longer
+  /// and some i16 instructions are slow.
   virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
     // By default, assume all legal types are desirable.
     return isTypeLegal(VT);
   }
 
-  /// isDesirableToPromoteOp - Return true if it is profitable for dag combiner
-  /// to transform a floating point op of specified opcode to a equivalent op of
-  /// an integer type. e.g. f32 load -> i32 load can be profitable on ARM.
+  /// Return true if it is profitable for dag combiner to transform a floating
+  /// point op of specified opcode to a equivalent op of an integer
+  /// type. e.g. f32 load -> i32 load can be profitable on ARM.
   virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
                                                  EVT /*VT*/) const {
     return false;
   }
 
-  /// IsDesirableToPromoteOp - This method query the target whether it is
-  /// beneficial for dag combiner to promote the specified node. If true, it
-  /// should return the desired promotion type by reference.
+  /// This method query the target whether it is beneficial for dag combiner to
+  /// promote the specified node. If true, it should return the desired
+  /// promotion type by reference.
   virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
     return false;
   }
@@ -1890,11 +1835,10 @@ public:
   // the SelectionDAGBuilder code knows how to lower these.
   //
 
-  /// LowerFormalArguments - This hook must be implemented to lower the
-  /// incoming (formal) arguments, described by the Ins array, into the
-  /// specified DAG. The implementation should fill in the InVals array
-  /// with legal-type argument values, and return the resulting token
-  /// chain value.
+  /// This hook must be implemented to lower the incoming (formal) arguments,
+  /// described by the Ins array, into the specified DAG. The implementation
+  /// should fill in the InVals array with legal-type argument values, and
+  /// return the resulting token chain value.
   ///
   virtual SDValue
     LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
@@ -1923,10 +1867,10 @@ public:
   };
   typedef std::vector<ArgListEntry> ArgListTy;
 
-  /// CallLoweringInfo - This structure contains all information that is
-  /// necessary for lowering calls. It is passed to TLI::LowerCallTo when the
-  /// SelectionDAG builder needs to lower a call, and targets will see this
-  /// struct in their LowerCall implementation.
+  /// This structure contains all information that is necessary for lowering
+  /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
+  /// needs to lower a call, and targets will see this struct in their LowerCall
+  /// implementation.
   struct CallLoweringInfo {
     SDValue Chain;
     Type *RetTy;
@@ -1953,8 +1897,7 @@ public:
     SmallVector<ISD::InputArg, 32> Ins;
 
 
-    /// CallLoweringInfo - Constructs a call lowering context based on the
-    /// ImmutableCallSite \p cs.
+    /// Constructs a call lowering context based on the ImmutableCallSite \p cs.
     CallLoweringInfo(SDValue chain, Type *retTy,
                      FunctionType *FTy, bool isTailCall, SDValue callee,
                      ArgListTy &args, SelectionDAG &dag, SDLoc dl,
@@ -1968,8 +1911,8 @@ public:
       CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag),
       DL(dl), CS(&cs) {}
 
-    /// CallLoweringInfo - Constructs a call lowering context based on the
-    /// provided call information.
+    /// Constructs a call lowering context based on the provided call
+    /// information.
     CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt,
                      bool isVarArg, bool isInReg, unsigned numFixedArgs,
                      CallingConv::ID callConv, bool isTailCall,
@@ -1982,32 +1925,29 @@ public:
       Args(args), DAG(dag), DL(dl), CS(NULL) {}
   };
 
-  /// LowerCallTo - This function lowers an abstract call to a function into an
-  /// actual call.  This returns a pair of operands.  The first element is the
-  /// return value for the function (if RetTy is not VoidTy).  The second
-  /// element is the outgoing token chain. It calls LowerCall to do the actual
-  /// lowering.
+  /// This function lowers an abstract call to a function into an actual call.
+  /// This returns a pair of operands.  The first element is the return value
+  /// for the function (if RetTy is not VoidTy).  The second element is the
+  /// outgoing token chain. It calls LowerCall to do the actual lowering.
   std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
 
-  /// LowerCall - This hook must be implemented to lower calls into the
-  /// the specified DAG. The outgoing arguments to the call are described
-  /// by the Outs array, and the values to be returned by the call are
-  /// described by the Ins array. The implementation should fill in the
-  /// InVals array with legal-type return values from the call, and return
-  /// the resulting token chain value.
+  /// This hook must be implemented to lower calls into the the specified
+  /// DAG. The outgoing arguments to the call are described by the Outs array,
+  /// and the values to be returned by the call are described by the Ins
+  /// array. The implementation should fill in the InVals array with legal-type
+  /// return values from the call, and return the resulting token chain value.
   virtual SDValue
     LowerCall(CallLoweringInfo &/*CLI*/,
               SmallVectorImpl<SDValue> &/*InVals*/) const {
     llvm_unreachable("Not Implemented");
   }
 
-  /// HandleByVal - Target-specific cleanup for formal ByVal parameters.
+  /// Target-specific cleanup for formal ByVal parameters.
   virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
 
-  /// CanLowerReturn - This hook should be implemented to check whether the
-  /// return values described by the Outs array can fit into the return
-  /// registers.  If false is returned, an sret-demotion is performed.
-  ///
+  /// This hook should be implemented to check whether the return values
+  /// described by the Outs array can fit into the return registers.  If false
+  /// is returned, an sret-demotion is performed.
   virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
                               MachineFunction &/*MF*/, bool /*isVarArg*/,
                const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
@@ -2017,11 +1957,9 @@ public:
     return true;
   }
 
-  /// LowerReturn - This hook must be implemented to lower outgoing
-  /// return values, described by the Outs array, into the specified
-  /// DAG. The implementation should return the resulting token chain
-  /// value.
-  ///
+  /// This hook must be implemented to lower outgoing return values, described
+  /// by the Outs array, into the specified DAG. The implementation should
+  /// return the resulting token chain value.
   virtual SDValue
     LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
                 bool /*isVarArg*/,
@@ -2031,42 +1969,42 @@ public:
     llvm_unreachable("Not Implemented");
   }
 
-  /// isUsedByReturnOnly - Return true if result of the specified node is used
-  /// by a return node only. It also compute and return the input chain for the
-  /// tail call.
-  /// This is used to determine whether it is possible
-  /// to codegen a libcall as tail call at legalization time.
+  /// Return true if result of the specified node is used by a return node
+  /// only. It also compute and return the input chain for the tail call.
+  ///
+  /// This is used to determine whether it is possible to codegen a libcall as
+  /// tail call at legalization time.
   virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
     return false;
   }
 
-  /// mayBeEmittedAsTailCall - Return true if the target may be able emit the
-  /// call instruction as a tail call. This is used by optimization passes to
-  /// determine if it's profitable to duplicate return instructions to enable
-  /// tailcall optimization.
+  /// Return true if the target may be able emit the call instruction as a tail
+  /// call. This is used by optimization passes to determine if it's profitable
+  /// to duplicate return instructions to enable tailcall optimization.
   virtual bool mayBeEmittedAsTailCall(CallInst *) const {
     return false;
   }
 
-  /// getTypeForExtArgOrReturn - Return the type that should be used to zero or
-  /// sign extend a zeroext/signext integer argument or return value.
-  /// FIXME: Most C calling convention requires the return type to be promoted,
-  /// but this is not true all the time, e.g. i1 on x86-64. It is also not
-  /// necessary for non-C calling conventions. The frontend should handle this
-  /// and include all of the necessary information.
+  /// Return the type that should be used to zero or sign extend a
+  /// zeroext/signext integer argument or return value.  FIXME: Most C calling
+  /// convention requires the return type to be promoted, but this is not true
+  /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
+  /// calling conventions. The frontend should handle this and include all of
+  /// the necessary information.
   virtual MVT getTypeForExtArgOrReturn(MVT VT,
                                        ISD::NodeType /*ExtendKind*/) const {
     MVT MinVT = getRegisterType(MVT::i32);
     return VT.bitsLT(MinVT) ? MinVT : VT;
   }
 
-  /// LowerOperationWrapper - This callback is invoked by the type legalizer
-  /// to legalize nodes with an illegal operand type but legal result types.
-  /// It replaces the LowerOperation callback in the type Legalizer.
-  /// The reason we can not do away with LowerOperation entirely is that
-  /// LegalizeDAG isn't yet ready to use this callback.
+  /// This callback is invoked by the type legalizer to legalize nodes with an
+  /// illegal operand type but legal result types.  It replaces the
+  /// LowerOperation callback in the type Legalizer.  The reason we can not do
+  /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
+  /// use this callback.
+  ///
   /// TODO: Consider merging with ReplaceNodeResults.
-
+  ///
   /// The target places new result values for the node in Results (their number
   /// and types must exactly match those of the original return values of
   /// the node), or leaves Results empty, which indicates that the node is not
@@ -2076,19 +2014,19 @@ public:
                                      SmallVectorImpl<SDValue> &Results,
                                      SelectionDAG &DAG) const;
 
-  /// LowerOperation - This callback is invoked for operations that are
-  /// unsupported by the target, which are registered to use 'custom' lowering,
-  /// and whose defined values are all legal.
-  /// If the target has no operations that require custom lowering, it need not
-  /// implement this.  The default implementation of this aborts.
+  /// This callback is invoked for operations that are unsupported by the
+  /// target, which are registered to use 'custom' lowering, and whose defined
+  /// values are all legal.  If the target has no operations that require custom
+  /// lowering, it need not implement this.  The default implementation of this
+  /// aborts.
   virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
 
-  /// ReplaceNodeResults - This callback is invoked when a node result type is
-  /// illegal for the target, and the operation was registered to use 'custom'
-  /// lowering for that result type.  The target places new result values for
-  /// the node in Results (their number and types must exactly match those of
-  /// the original return values of the node), or leaves Results empty, which
-  /// indicates that the node is not to be custom lowered after all.
+  /// This callback is invoked when a node result type is illegal for the
+  /// target, and the operation was registered to use 'custom' lowering for that
+  /// result type.  The target places new result values for the node in Results
+  /// (their number and types must exactly match those of the original return
+  /// values of the node), or leaves Results empty, which indicates that the
+  /// node is not to be custom lowered after all.
   ///
   /// If the target has no operations that require custom lowering, it need not
   /// implement this.  The default implementation aborts.
@@ -2098,12 +2036,11 @@ public:
     llvm_unreachable("ReplaceNodeResults not implemented for this target!");
   }
 
-  /// getTargetNodeName() - This method returns the name of a target specific
-  /// DAG node.
+  /// This method returns the name of a target specific DAG node.
   virtual const char *getTargetNodeName(unsigned Opcode) const;
 
-  /// createFastISel - This method returns a target specific FastISel object,
-  /// or null if the target does not support "fast" ISel.
+  /// This method returns a target specific FastISel object, or null if the
+  /// target does not support "fast" ISel.
   virtual FastISel *createFastISel(FunctionLoweringInfo &,
                                    const TargetLibraryInfo *) const {
     return 0;
@@ -2113,10 +2050,10 @@ public:
   // Inline Asm Support hooks
   //
 
-  /// ExpandInlineAsm - This hook allows the target to expand an inline asm
-  /// call to be explicit llvm code if it wants to.  This is useful for
-  /// turning simple inline asms into LLVM intrinsics, which gives the
-  /// compiler more information about the behavior of the code.
+  /// This hook allows the target to expand an inline asm call to be explicit
+  /// llvm code if it wants to.  This is useful for turning simple inline asms
+  /// into LLVM intrinsics, which gives the compiler more information about the
+  /// behavior of the code.
   virtual bool ExpandInlineAsm(CallInst *) const {
     return false;
   }
@@ -2145,32 +2082,31 @@ public:
     CW_Default      = CW_Okay     // Default or don't know type.
   };
 
-  /// AsmOperandInfo - This contains information for each constraint that we are
-  /// lowering.
+  /// This contains information for each constraint that we are lowering.
   struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
-    /// ConstraintCode - This contains the actual string for the code, like "m".
-    /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
-    /// most closely matches the operand.
+    /// This contains the actual string for the code, like "m".  TargetLowering
+    /// picks the 'best' code from ConstraintInfo::Codes that most closely
+    /// matches the operand.
     std::string ConstraintCode;
 
-    /// ConstraintType - Information about the constraint code, e.g. Register,
-    /// RegisterClass, Memory, Other, Unknown.
+    /// Information about the constraint code, e.g. Register, RegisterClass,
+    /// Memory, Other, Unknown.
     TargetLowering::ConstraintType ConstraintType;
 
-    /// CallOperandval - If this is the result output operand or a
-    /// clobber, this is null, otherwise it is the incoming operand to the
-    /// CallInst.  This gets modified as the asm is processed.
+    /// If this is the result output operand or a clobber, this is null,
+    /// otherwise it is the incoming operand to the CallInst.  This gets
+    /// modified as the asm is processed.
     Value *CallOperandVal;
 
-    /// ConstraintVT - The ValueType for the operand value.
+    /// The ValueType for the operand value.
     MVT ConstraintVT;
 
-    /// isMatchingInputConstraint - Return true of this is an input operand that
-    /// is a matching constraint like "4".
+    /// Return true of this is an input operand that is a matching constraint
+    /// like "4".
     bool isMatchingInputConstraint() const;
 
-    /// getMatchedOperand - If this is an input matching constraint, this method
-    /// returns the output operand it matches.
+    /// If this is an input matching constraint, this method returns the output
+    /// operand it matches.
     unsigned getMatchedOperand() const;
 
     /// Copy constructor for copying from an AsmOperandInfo.
@@ -2192,11 +2128,10 @@ public:
 
   typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
 
-  /// ParseConstraints - Split up the constraint string from the inline
-  /// assembly value into the specific constraints and their prefixes,
-  /// and also tie in the associated operand values.
-  /// If this returns an empty vector, and if the constraint string itself
-  /// isn't empty, there was an error parsing.
+  /// Split up the constraint string from the inline assembly value into the
+  /// specific constraints and their prefixes, and also tie in the associated
+  /// operand values.  If this returns an empty vector, and if the constraint
+  /// string itself isn't empty, there was an error parsing.
   virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
 
   /// Examine constraint type and operand type and determine a weight value.
@@ -2209,41 +2144,37 @@ public:
   virtual ConstraintWeight getSingleConstraintMatchWeight(
       AsmOperandInfo &info, const char *constraint) const;
 
-  /// ComputeConstraintToUse - Determines the constraint code and constraint
-  /// type to use for the specific AsmOperandInfo, setting
-  /// OpInfo.ConstraintCode and OpInfo.ConstraintType.  If the actual operand
-  /// being passed in is available, it can be passed in as Op, otherwise an
-  /// empty SDValue can be passed.
+  /// Determines the constraint code and constraint type to use for the specific
+  /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
+  /// If the actual operand being passed in is available, it can be passed in as
+  /// Op, otherwise an empty SDValue can be passed.
   virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
                                       SDValue Op,
                                       SelectionDAG *DAG = 0) const;
 
-  /// getConstraintType - Given a constraint, return the type of constraint it
-  /// is for this target.
+  /// Given a constraint, return the type of constraint it is for this target.
   virtual ConstraintType getConstraintType(const std::string &Constraint) const;
 
-  /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
-  /// {edx}), return the register number and the register class for the
-  /// register.
+  /// Given a physical register constraint (e.g.  {edx}), return the register
+  /// number and the register class for the register.
   ///
   /// Given a register class constraint, like 'r', if this corresponds directly
   /// to an LLVM register class, return a register of 0 and the register class
   /// pointer.
   ///
-  /// This should only be used for C_Register constraints.  On error,
-  /// this returns a register number of 0 and a null register class pointer..
+  /// This should only be used for C_Register constraints.  On error, this
+  /// returns a register number of 0 and a null register class pointer..
   virtual std::pair<unsigned, const TargetRegisterClass*>
     getRegForInlineAsmConstraint(const std::string &Constraint,
                                  MVT VT) const;
 
-  /// LowerXConstraint - try to replace an X constraint, which matches anything,
-  /// with another that has more specific requirements based on the type of the
-  /// corresponding operand.  This returns null if there is no replacement to
-  /// make.
+  /// Try to replace an X constraint, which matches anything, with another that
+  /// has more specific requirements based on the type of the corresponding
+  /// operand.  This returns null if there is no replacement to make.
   virtual const char *LowerXConstraint(EVT ConstraintVT) const;
 
-  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
-  /// vector.  If it is invalid, don't add anything to Ops.
+  /// Lower the specified operand into the Ops vector.  If it is invalid, don't
+  /// add anything to Ops.
   virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
                                             std::vector<SDValue> &Ops,
                                             SelectionDAG &DAG) const;
@@ -2262,26 +2193,26 @@ public:
   // Instruction Emitting Hooks
   //
 
-  // EmitInstrWithCustomInserter - This method should be implemented by targets
-  // that mark instructions with the 'usesCustomInserter' flag.  These
-  // instructions are special in various ways, which require special support to
-  // insert.  The specified MachineInstr is created but not inserted into any
-  // basic blocks, and this method is called to expand it into a sequence of
-  // instructions, potentially also creating new basic blocks and control flow.
+  // This method should be implemented by targets that mark instructions with
+  // the 'usesCustomInserter' flag.  These instructions are special in various
+  // ways, which require special support to insert.  The specified MachineInstr
+  // is created but not inserted into any basic blocks, and this method is
+  // called to expand it into a sequence of instructions, potentially also
+  // creating new basic blocks and control flow.
   virtual MachineBasicBlock *
     EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
 
-  /// AdjustInstrPostInstrSelection - This method should be implemented by
-  /// targets that mark instructions with the 'hasPostISelHook' flag. These
-  /// instructions must be adjusted after instruction selection by target hooks.
-  /// e.g. To fill in optional defs for ARM 's' setting instructions.
+  /// This method should be implemented by targets that mark instructions with
+  /// the 'hasPostISelHook' flag. These instructions must be adjusted after
+  /// instruction selection by target hooks.  e.g. To fill in optional defs for
+  /// ARM 's' setting instructions.
   virtual void
   AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
 };
 
-/// GetReturnInfo - Given an LLVM IR type and return type attributes,
-/// compute the return value EVTs and flags, and optionally also
-/// the offsets, if the return value is being lowered to memory.
+/// Given an LLVM IR type and return type attributes, compute the return value
+/// EVTs and flags, and optionally also the offsets, if the return value is
+/// being lowered to memory.
 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
                    SmallVectorImpl<ISD::OutputArg> &Outs,
                    const TargetLowering &TLI);