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| author | Hal Finkel <hfinkel@anl.gov> | 2012-08-04 14:10:46 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2012-08-04 14:10:46 +0000 |
| commit | 8cc3474f72388836fa4ca7d3622289fb9ee08b41 (patch) | |
| tree | ff2efb5d8b676af7332ad5a3df07759354943f3f /include/llvm/Target/TargetSelectionDAG.td | |
| parent | ad62e92279bc0b14c54db94dd794082c8b8edd9e (diff) | |
| download | external_llvm-8cc3474f72388836fa4ca7d3622289fb9ee08b41.zip external_llvm-8cc3474f72388836fa4ca7d3622289fb9ee08b41.tar.gz external_llvm-8cc3474f72388836fa4ca7d3622289fb9ee08b41.tar.bz2 | |
Add readcyclecounter lowering on PPC64.
On PPC64, this can be done with a simple TableGen pattern.
To enable this, I've added the (otherwise missing) readcyclecounter
SDNode definition to TargetSelectionDAG.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161302 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/Target/TargetSelectionDAG.td')
| -rw-r--r-- | include/llvm/Target/TargetSelectionDAG.td | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td index ff006b6..3f81c06 100644 --- a/include/llvm/Target/TargetSelectionDAG.td +++ b/include/llvm/Target/TargetSelectionDAG.td @@ -411,6 +411,9 @@ def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf, + [SDNPHasChain, SDNPSideEffect]>; + def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier, [SDNPHasChain, SDNPSideEffect]>; |