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authorBenjamin Kramer <benny.kra@googlemail.com>2011-07-14 21:47:18 +0000
committerBenjamin Kramer <benny.kra@googlemail.com>2011-07-14 21:47:18 +0000
commit5196c12e9fdec9ef3c63d96cb529c1c1cb732773 (patch)
tree78d2c0a828c34d649e022fc51e5af3a8ce29bd8d /include/llvm/Target
parent70d8fcfaa04eb20541b006a8fb97cbc1d3033cc4 (diff)
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Add a new field to MCOperandInfo that contains information about the type of the Operand.
- The actual values are from the MCOI::OperandType enum. - Teach tblgen to read it from the instruction definition. - This is a better implementation of the hacks in edis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135197 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/Target')
-rw-r--r--include/llvm/Target/Target.td3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index 360eea3..018ccbd 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -500,6 +500,7 @@ class Operand<ValueType ty> {
string EncoderMethod = "";
string DecoderMethod = "";
string AsmOperandLowerMethod = ?;
+ string OperandType = "OPERAND_UNKNOWN";
dag MIOperandInfo = (ops);
// ParserMatchClass - The "match class" that operands of this type fit
@@ -531,6 +532,7 @@ class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> {
AsmOperandClass ParserMatchClass;
}
+let OperandType = "OPERAND_IMMEDIATE" in {
def i1imm : Operand<i1>;
def i8imm : Operand<i8>;
def i16imm : Operand<i16>;
@@ -539,6 +541,7 @@ def i64imm : Operand<i64>;
def f32imm : Operand<f32>;
def f64imm : Operand<f64>;
+}
/// zero_reg definition - Special node to stand for the zero register.
///