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author | Craig Topper <craig.topper@gmail.com> | 2012-03-04 10:16:38 +0000 |
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committer | Craig Topper <craig.topper@gmail.com> | 2012-03-04 10:16:38 +0000 |
commit | b6632ba380cf624e60fe16b03d6e21b05dd07724 (patch) | |
tree | 5b3ca53e138cd22a7b04e0e034b0a952d0972de7 /include/llvm/Target | |
parent | 015f228861ef9b337366f92f637d4e8d624bb006 (diff) | |
download | external_llvm-b6632ba380cf624e60fe16b03d6e21b05dd07724.zip external_llvm-b6632ba380cf624e60fe16b03d6e21b05dd07724.tar.gz external_llvm-b6632ba380cf624e60fe16b03d6e21b05dd07724.tar.bz2 |
Use uint16_t instead of unsigned to store registers in reg classes. Reduces static data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151998 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/Target')
-rw-r--r-- | include/llvm/Target/TargetRegisterInfo.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h index 5bbc450..1f940ae 100644 --- a/include/llvm/Target/TargetRegisterInfo.h +++ b/include/llvm/Target/TargetRegisterInfo.h @@ -34,8 +34,8 @@ class raw_ostream; class TargetRegisterClass { public: - typedef const unsigned* iterator; - typedef const unsigned* const_iterator; + typedef const uint16_t* iterator; + typedef const uint16_t* const_iterator; typedef const MVT::SimpleValueType* vt_iterator; typedef const TargetRegisterClass* const * sc_iterator; @@ -45,7 +45,7 @@ public: const unsigned *SubClassMask; const sc_iterator SuperClasses; const sc_iterator SuperRegClasses; - ArrayRef<unsigned> (*OrderFunc)(const MachineFunction&); + ArrayRef<uint16_t> (*OrderFunc)(const MachineFunction&); /// getID() - Return the register class ID number. /// @@ -190,7 +190,7 @@ public: /// /// By default, this method returns all registers in the class. /// - ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const { + ArrayRef<uint16_t> getRawAllocationOrder(const MachineFunction &MF) const { return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs()); } }; @@ -514,7 +514,7 @@ public: /// /// Register allocators need only call this function to resolve /// target-dependent hints, but it should work without hinting as well. - virtual ArrayRef<unsigned> + virtual ArrayRef<uint16_t> getRawAllocationOrder(const TargetRegisterClass *RC, unsigned HintType, unsigned HintReg, const MachineFunction &MF) const { |