Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."

This reverts commit 104654.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 11 insertions, 17 deletions

diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index ca551e5..9e0ad6f 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -54,23 +54,6 @@ class Register<string n> {
   // not [AX, AH, AL].
   list<Register> SubRegs = [];
 
-  // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
-  // to address it. Sub-sub-register indices are automatically inherited from
-  // SubRegs.
-  list<SubRegIndex> SubRegIndices = [];
-
-  // CompositeIndices - Specify subreg indices that don't correspond directly to
-  // a register in SubRegs and are not inherited. The following formats are
-  // supported:
-  //
-  // (a)     Identity  - Reg:a == Reg
-  // (a b)   Alias     - Reg:a == Reg:b
-  // (a b,c) Composite - Reg:a == (Reg:b):c
-  //
-  // This can be used to disambiguate a sub-sub-register that exists in more
-  // than one subregister and other weird stuff.
-  list<dag> CompositeIndices = [];
-
   // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
   // These values can be determined by locating the <target>.h file in the
   // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES.  The
@@ -90,6 +73,17 @@ class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
   let SubRegs = subregs;
 }
 
+// SubRegSet - This can be used to define a specific mapping of registers to
+// indices, for use as named subregs of a particular physical register.  Each
+// register in 'subregs' becomes an addressable subregister at index 'n' of the
+// corresponding register in 'regs'.
+class SubRegSet<SubRegIndex n, list<Register> regs, list<Register> subregs> {
+  SubRegIndex Index = n;
+  
+  list<Register> From = regs;
+  list<Register> To = subregs;
+}
+
 // RegisterClass - Now that all of the registers are defined, and aliases
 // between registers are defined, specify which registers belong to which
 // register classes.  This also defines the default allocation order of