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authorAnton Korobeynikov <asl@math.spbu.ru>2010-03-14 18:42:15 +0000
committerAnton Korobeynikov <asl@math.spbu.ru>2010-03-14 18:42:15 +0000
commitbe5b032e4b06ae001098856c2dc4ebca41528132 (patch)
treed00d7df9b4fb5f7c0b89f11b1f4ba92da31bef51 /include/llvm
parentfeacf28cf803373b48a9af7995218728957f5403 (diff)
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Add DAG nodes to represent FP16 <-> FP32 intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98500 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm')
-rw-r--r--include/llvm/CodeGen/SelectionDAGNodes.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index e61672d..c16a48a 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -439,6 +439,12 @@ namespace ISD {
// 5) ISD::CvtCode indicating the type of conversion to do
CONVERT_RNDSAT,
+ // FP16_TO_FP32, FP32_TO_FP16 - These operators are used to perform
+ // promotions and truncation for half-precision (16 bit) floating
+ // numbers. We need special nodes since FP16 is a storage-only type with
+ // special semantics of operations.
+ FP16_TO_FP32, FP32_TO_FP16,
+
// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
// FLOG, FLOG2, FLOG10, FEXP, FEXP2,
// FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary floating