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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-26 17:27:12 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-26 17:27:12 +0000 |
commit | ca561ffcf320e9dbfafcac5efcee81471f3259c3 (patch) | |
tree | 4f981f60d7df5e4438c803fb06447d66c4c599a0 /include/llvm | |
parent | 90346e2261a1788a1e353c6b8e7e1818a3fd37c9 (diff) | |
download | external_llvm-ca561ffcf320e9dbfafcac5efcee81471f3259c3.zip external_llvm-ca561ffcf320e9dbfafcac5efcee81471f3259c3.tar.gz external_llvm-ca561ffcf320e9dbfafcac5efcee81471f3259c3.tar.bz2 |
Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm')
-rw-r--r-- | include/llvm/Target/Target.td | 28 |
1 files changed, 17 insertions, 11 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index 9e0ad6f..ca551e5 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -54,6 +54,23 @@ class Register<string n> { // not [AX, AH, AL]. list<Register> SubRegs = []; + // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used + // to address it. Sub-sub-register indices are automatically inherited from + // SubRegs. + list<SubRegIndex> SubRegIndices = []; + + // CompositeIndices - Specify subreg indices that don't correspond directly to + // a register in SubRegs and are not inherited. The following formats are + // supported: + // + // (a) Identity - Reg:a == Reg + // (a b) Alias - Reg:a == Reg:b + // (a b,c) Composite - Reg:a == (Reg:b):c + // + // This can be used to disambiguate a sub-sub-register that exists in more + // than one subregister and other weird stuff. + list<dag> CompositeIndices = []; + // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. // These values can be determined by locating the <target>.h file in the // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The @@ -73,17 +90,6 @@ class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { let SubRegs = subregs; } -// SubRegSet - This can be used to define a specific mapping of registers to -// indices, for use as named subregs of a particular physical register. Each -// register in 'subregs' becomes an addressable subregister at index 'n' of the -// corresponding register in 'regs'. -class SubRegSet<SubRegIndex n, list<Register> regs, list<Register> subregs> { - SubRegIndex Index = n; - - list<Register> From = regs; - list<Register> To = subregs; -} - // RegisterClass - Now that all of the registers are defined, and aliases // between registers are defined, specify which registers belong to which // register classes. This also defines the default allocation order of |