Capture information about whether the target instructions have delay slots

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16550 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 9 insertions, 0 deletions

diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index d5f4b94..fe4922a 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -48,6 +48,7 @@ const unsigned M_BRANCH_FLAG		= 1 << 1;
 const unsigned M_CALL_FLAG		= 1 << 2;
 const unsigned M_RET_FLAG		= 1 << 3;
 const unsigned M_BARRIER_FLAG           = 1 << 4;
+const unsigned M_DELAY_SLOT             = 1 << 5;
 const unsigned M_CC_FLAG		= 1 << 6;
 const unsigned M_LOAD_FLAG		= 1 << 10;
 const unsigned M_STORE_FLAG		= 1 << 12;
@@ -193,6 +194,7 @@ public:
   bool isBarrier(MachineOpCode Opcode) const {
     return get(Opcode).Flags & M_BARRIER_FLAG;
   }
+
   bool isCall(MachineOpCode Opcode) const {
     return get(Opcode).Flags & M_CALL_FLAG;
   }
@@ -202,6 +204,13 @@ public:
   bool isStore(MachineOpCode Opcode) const {
     return get(Opcode).Flags & M_STORE_FLAG;
   }
+
+  /// hasDelaySlot - Returns true if the specified instruction has a delay slot
+  /// which must be filled by the code generator.
+  bool hasDelaySlot(unsigned Opcode) const {
+    return get(Opcode).Flags & M_DELAY_SLOT;
+  }
+
   virtual bool hasResultInterlock(MachineOpCode Opcode) const {
     return true;
   }