Change createPostRAScheduler so it can be turned off at llc -O1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 12 insertions, 6 deletions

diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h
index 1e7115e..d0d6103 100644
--- a/include/llvm/CodeGen/Passes.h
+++ b/include/llvm/CodeGen/Passes.h
@@ -15,13 +15,13 @@
 #ifndef LLVM_CODEGEN_PASSES_H
 #define LLVM_CODEGEN_PASSES_H
 
+#include "llvm/Target/TargetMachine.h"
 #include <string>
 
 namespace llvm {
 
   class FunctionPass;
   class PassInfo;
-  class TargetMachine;
   class TargetLowering;
   class RegisterCoalescer;
   class raw_ostream;
@@ -119,8 +119,9 @@ namespace llvm {
   ///
   FunctionPass *createLowerSubregsPass();
 
-  /// createPostRAScheduler - under development.
-  FunctionPass *createPostRAScheduler();
+  /// createPostRAScheduler - This pass performs post register allocation
+  /// scheduling.
+  FunctionPass *createPostRAScheduler(CodeGenOpt::Level OptLevel);
 
   /// BranchFolding Pass - This pass performs machine code CFG based
   /// optimizations to delete branches to branches, eliminate branches to
diff --git a/include/llvm/Target/TargetSubtarget.h b/include/llvm/Target/TargetSubtarget.h
index ac094f6..5edb86f 100644
--- a/include/llvm/Target/TargetSubtarget.h
+++ b/include/llvm/Target/TargetSubtarget.h
@@ -14,6 +14,8 @@
 #ifndef LLVM_TARGET_TARGETSUBTARGET_H
 #define LLVM_TARGET_TARGETSUBTARGET_H
 
+#include "llvm/Target/TargetMachine.h"
+
 namespace llvm {
 
 class SDep;
@@ -39,9 +41,12 @@ public:
   /// should be attempted.
   virtual unsigned getSpecialAddressLatency() const { return 0; }
 
-  // enablePostRAScheduler - Return true to enable
-  // post-register-allocation scheduling.
-  virtual bool enablePostRAScheduler() const { return false; }
+  // enablePostRAScheduler - If the target can benefit from post-regalloc
+  // scheduling and the specified optimization level meets the requirement
+  // return true to enable post-register-allocation scheduling.
+  virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
+    return false;
+  }
 
   // adjustSchedDependency - Perform target specific adjustments to
   // the latency of a schedule dependency.