Replace the tablegen RegisterClass field SubRegClassList with an alist-like data

structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 3 insertions, 6 deletions

diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index 94430bc..b9ec987 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -125,9 +125,9 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
   //
   list<Register> MemberList = regList;
   
-  // SubClassList - Specify which register classes correspond to subregisters
-  // of this class. The order should be by subregister set index.
-  list<RegisterClass> SubRegClassList = [];
+  // SubRegClasses - Specify the register class of subregisters as a list of
+  // dags: (RegClass SubRegIndex, SubRegindex, ...)
+  list<dag> SubRegClasses = [];
 
   // MethodProtos/MethodBodies - These members can be used to insert arbitrary
   // code into a generated register class.   The normal usage of this is to 
diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h
index aeb669d..053168a 100644
--- a/include/llvm/Target/TargetRegisterInfo.h
+++ b/include/llvm/Target/TargetRegisterInfo.h
@@ -152,9 +152,6 @@ public:
   /// index SubIdx, or NULL if no such class exists.
   const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
     assert(SubIdx>0 && "Invalid subregister index");
-    for (unsigned s = 0; s != SubIdx-1; ++s)
-      if (!SubRegClasses[s])
-        return NULL;
     return SubRegClasses[SubIdx-1];
   }