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author | Evan Cheng <evan.cheng@apple.com> | 2010-05-20 23:26:43 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2010-05-20 23:26:43 +0000 |
commit | 1cc3984148be113c6e5e470f23c9ddbd37679c5f (patch) | |
tree | 29e4aa36a65bfff658e868fdf3191f964de22730 /include | |
parent | 0fe46d9b480ab4851e1fc8bc589d1ed9c8b2a70e (diff) | |
download | external_llvm-1cc3984148be113c6e5e470f23c9ddbd37679c5f.zip external_llvm-1cc3984148be113c6e5e470f23c9ddbd37679c5f.tar.gz external_llvm-1cc3984148be113c6e5e470f23c9ddbd37679c5f.tar.bz2 |
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r-- | include/llvm/CodeGen/ScheduleDAG.h | 9 | ||||
-rw-r--r-- | include/llvm/Target/TargetLowering.h | 7 | ||||
-rw-r--r-- | include/llvm/Target/TargetMachine.h | 1 |
3 files changed, 15 insertions, 2 deletions
diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 3c59a5a..9478806 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -16,6 +16,7 @@ #define LLVM_CODEGEN_SCHEDULEDAG_H #include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/Target/TargetMachine.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/GraphTraits.h" @@ -238,7 +239,7 @@ namespace llvm { typedef SmallVector<SDep, 4>::iterator succ_iterator; typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator; typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator; - + unsigned NodeNum; // Entry # of node in the node vector. unsigned NodeQueueId; // Queue id of node. unsigned short Latency; // Node latency. @@ -255,6 +256,7 @@ namespace llvm { bool isScheduled : 1; // True once scheduled. bool isScheduleHigh : 1; // True if preferable to schedule high. bool isCloned : 1; // True if this node has been cloned. + Sched::Preference SchedulingPref; // Scheduling preference. SmallVector<MachineInstr*, 4> DbgInstrList; // dbg_values referencing this. private: @@ -275,6 +277,7 @@ namespace llvm { hasPhysRegDefs(false), hasPhysRegClobbers(false), isPending(false), isAvailable(false), isScheduled(false), isScheduleHigh(false), isCloned(false), + SchedulingPref(Sched::None), isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), CopyDstRC(NULL), CopySrcRC(NULL) {} @@ -287,6 +290,7 @@ namespace llvm { hasPhysRegDefs(false), hasPhysRegClobbers(false), isPending(false), isAvailable(false), isScheduled(false), isScheduleHigh(false), isCloned(false), + SchedulingPref(Sched::None), isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), CopyDstRC(NULL), CopySrcRC(NULL) {} @@ -298,6 +302,7 @@ namespace llvm { hasPhysRegDefs(false), hasPhysRegClobbers(false), isPending(false), isAvailable(false), isScheduled(false), isScheduleHigh(false), isCloned(false), + SchedulingPref(Sched::None), isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), CopyDstRC(NULL), CopySrcRC(NULL) {} @@ -390,7 +395,7 @@ namespace llvm { return true; return false; } - + void dump(const ScheduleDAG *G) const; void dumpAll(const ScheduleDAG *G) const; void print(raw_ostream &O, const ScheduleDAG *G) const; diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index b06a7b9..5efebe6 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -149,6 +149,13 @@ public: return SchedPreferenceInfo; } + /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to + /// different scheduling heuristics for different nodes. This function returns + /// the preference (or none) for the given node. + virtual Sched::Preference getSchedulingPreference(SDNode *N) const { + return Sched::None; + } + /// getRegClassFor - Return the register class that should be used for the /// specified value type. virtual TargetRegisterClass *getRegClassFor(EVT VT) const { diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h index a89288d..bffba18 100644 --- a/include/llvm/Target/TargetMachine.h +++ b/include/llvm/Target/TargetMachine.h @@ -72,6 +72,7 @@ namespace CodeGenOpt { namespace Sched { enum Preference { + None, // No preference Latency, // Scheduling for shortest total latency. RegPressure, // Scheduling for lowest register pressure. Hybrid // Scheduling for both latency and register pressure. |