Teach if-converter to be more careful with predicating instructions that would

take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 15 insertions, 7 deletions

diff --git a/include/llvm/CodeGen/PostRAHazardRecognizer.h b/include/llvm/CodeGen/PostRAHazardRecognizer.h
index 24d73cb..4160384 100644
--- a/include/llvm/CodeGen/PostRAHazardRecognizer.h
+++ b/include/llvm/CodeGen/PostRAHazardRecognizer.h
@@ -75,13 +75,13 @@ class PostRAHazardRecognizer : public ScheduleHazardRecognizer {
   };
 
   // Itinerary data for the target.
-  const InstrItineraryData &ItinData;
+  const InstrItineraryData *ItinData;
 
   ScoreBoard ReservedScoreboard;
   ScoreBoard RequiredScoreboard;
 
 public:
-  PostRAHazardRecognizer(const InstrItineraryData &ItinData);
+  PostRAHazardRecognizer(const InstrItineraryData *ItinData);
 
   virtual HazardType getHazardType(SUnit *SU);
   virtual void Reset();
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index 7ce1f71..844b965 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -575,7 +575,7 @@ public:
   /// to use for this target when scheduling the machine instructions after
   /// register allocation.
   virtual ScheduleHazardRecognizer*
-  CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const = 0;
+  CreateTargetPostRAHazardRecognizer(const InstrItineraryData*) const = 0;
 
   /// AnalyzeCompare - For a comparison instruction, return the source register
   /// in SrcReg and the value it compares against in CmpValue. Return true if
@@ -595,7 +595,7 @@ public:
   /// getNumMicroOps - Return the number of u-operations the given machine
   /// instruction will be decoded to on the target cpu.
   virtual unsigned getNumMicroOps(const MachineInstr *MI,
-                                  const InstrItineraryData &ItinData) const;
+                                  const InstrItineraryData *ItinData) const;
 };
 
 /// TargetInstrInfoImpl - This is the default implementation of
@@ -631,7 +631,7 @@ public:
                                     const MachineFunction &MF) const;
 
   virtual ScheduleHazardRecognizer *
-  CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const;
+  CreateTargetPostRAHazardRecognizer(const InstrItineraryData*) const;
 };
 
 } // End llvm namespace
diff --git a/include/llvm/Target/TargetInstrItineraries.h b/include/llvm/Target/TargetInstrItineraries.h
index ae3e621..ae156ea 100644
--- a/include/llvm/Target/TargetInstrItineraries.h
+++ b/include/llvm/Target/TargetInstrItineraries.h
@@ -181,6 +181,14 @@ public:
 
     return (int)OperandCycles[FirstIdx + OperandIdx];
   }
+
+  /// isMicroCoded - Return true if the instructions in the given class decode
+  /// to more than one micro-ops.
+  bool isMicroCoded(unsigned ItinClassIndx) const {
+    if (isEmpty())
+      return false;
+    return Itineratries[ItinClassIndx].NumMicroOps != 1;
+  }
 };
 
 
diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h
index 42e99e0..426338f 100644
--- a/include/llvm/Target/TargetMachine.h
+++ b/include/llvm/Target/TargetMachine.h
@@ -152,8 +152,8 @@ public:
   /// getInstrItineraryData - Returns instruction itinerary data for the target
   /// or specific subtarget.
   ///
-  virtual const InstrItineraryData getInstrItineraryData() const {  
-    return InstrItineraryData();
+  virtual const InstrItineraryData *getInstrItineraryData() const {  
+    return 0;
   }
 
   /// getELFWriterInfo - If this target supports an ELF writer, return