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author | Vikram S. Adve <vadve@cs.uiuc.edu> | 2001-11-09 02:11:25 +0000 |
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committer | Vikram S. Adve <vadve@cs.uiuc.edu> | 2001-11-09 02:11:25 +0000 |
commit | 40abd3fab81a8e81ebde3d54825b1d71b2db50ac (patch) | |
tree | f2e816a6d6f8bd05b7fbbe6b41cd63af64106900 /include | |
parent | 4938d4528f80dd015c58dec9d6d72bc27bf26bbd (diff) | |
download | external_llvm-40abd3fab81a8e81ebde3d54825b1d71b2db50ac.zip external_llvm-40abd3fab81a8e81ebde3d54825b1d71b2db50ac.tar.gz external_llvm-40abd3fab81a8e81ebde3d54825b1d71b2db50ac.tar.bz2 |
Cache parameters for target machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1222 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r-- | include/llvm/Target/TargetCacheInfo.h | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/include/llvm/Target/TargetCacheInfo.h b/include/llvm/Target/TargetCacheInfo.h new file mode 100644 index 0000000..67b549c --- /dev/null +++ b/include/llvm/Target/TargetCacheInfo.h @@ -0,0 +1,67 @@ +// $Id$ -*-c++-*- +//*************************************************************************** +// File: +// MachineCacheInfo.h +// +// Purpose: +// Describes properties of the target cache architecture. +//**************************************************************************/ + +#ifndef LLVM_TARGET_MACHINECACHEINFO_H +#define LLVM_TARGET_MACHINECACHEINFO_H + +#include "llvm/Target/TargetMachine.h" +#include "llvm/Support/DataTypes.h" +#include <vector> + + +//--------------------------------------------------------------------------- +// class MachineCacheInfo +// +// Purpose: +// Describes properties of the target cache architecture. +//--------------------------------------------------------------------------- + +class MachineCacheInfo : public NonCopyableV { +public: + const TargetMachine& target; + +protected: + unsigned int numLevels; + vector<unsigned short> cacheLineSizes; + vector<unsigned int> cacheSizes; + vector<unsigned short> cacheAssoc; + +public: + /*ctor*/ MachineCacheInfo (const TargetMachine& tgt); + /*dtor*/ virtual ~MachineCacheInfo () {} + + // Default parameters are: + // NumLevels = 2 + // L1: LineSize 16, Cache Size 32KB, Direct-mapped (assoc = 1) + // L2: LineSize 32, Cache Size 1 MB, 4-way associative + // NOTE: Cache levels are numbered from 1 as above, not from 0. + // + virtual void Initialize (); // subclass to override defaults + + unsigned int getNumCacheLevels () const { + return numLevels; + } + unsigned short getCacheLineSize (unsigned level) const { + assert(level <= cacheLineSizes.size() && "Invalid cache level"); + return cacheLineSizes[level-1]; + } + unsigned int getCacheSize (unsigned level) const { + assert(level <= cacheSizes.size() && "Invalid cache level"); + return cacheSizes[level-1]; + } + unsigned short getCacheAssoc (unsigned level) const { + assert(level <= cacheAssoc.size() && "Invalid cache level"); + return cacheAssoc[level]; + } +}; + + +//--------------------------------------------------------------------------- + +#endif |