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author | Mon P Wang <wangmp@apple.com> | 2008-05-05 19:05:59 +0000 |
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committer | Mon P Wang <wangmp@apple.com> | 2008-05-05 19:05:59 +0000 |
commit | 63307c335aa08b0d6a75f81d64d79af7e90eb78b (patch) | |
tree | da7531194465dc141c0d26ff68d1989c462b2c89 /include | |
parent | 94bbdc8c254e259eff22eb5d6a1012fc1438fb45 (diff) | |
download | external_llvm-63307c335aa08b0d6a75f81d64d79af7e90eb78b.zip external_llvm-63307c335aa08b0d6a75f81d64d79af7e90eb78b.tar.gz external_llvm-63307c335aa08b0d6a75f81d64d79af7e90eb78b.tar.bz2 |
Added addition atomic instrinsics and, or, xor, min, and max.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50663 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r-- | include/llvm/CodeGen/MachineBasicBlock.h | 5 | ||||
-rw-r--r-- | include/llvm/CodeGen/SelectionDAGNodes.h | 18 | ||||
-rw-r--r-- | include/llvm/Intrinsics.td | 70 | ||||
-rw-r--r-- | include/llvm/Target/TargetLowering.h | 7 |
4 files changed, 83 insertions, 17 deletions
diff --git a/include/llvm/CodeGen/MachineBasicBlock.h b/include/llvm/CodeGen/MachineBasicBlock.h index 0b3173c..6fbe170 100644 --- a/include/llvm/CodeGen/MachineBasicBlock.h +++ b/include/llvm/CodeGen/MachineBasicBlock.h @@ -236,6 +236,11 @@ public: /// succ_iterator removeSuccessor(succ_iterator I); + /// transferSuccessors - Transfers all the successors from MBB to this + /// machine basic block (i.e., copies all the successors fromMBB and + /// remove all the successors fromBB). + void transferSuccessors(MachineBasicBlock *fromMBB); + /// isSuccessor - Return true if the specified MBB is a successor of this /// block. bool isSuccessor(MachineBasicBlock *MBB) const; diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index c9872cf..a02f7b9 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -594,6 +594,24 @@ namespace ISD { // the return is always the original value in *ptr ATOMIC_SWAP, + // Val, OUTCHAIN = ATOMIC_LSS(INCHAIN, ptr, amt) + // this corresponds to the atomic.lss intrinsic. + // *ptr - amt is stored to *ptr atomically. + // the return is always the original value in *ptr + ATOMIC_LSS, + + // Val, OUTCHAIN = ATOMIC_L[OpName]S(INCHAIN, ptr, amt) + // this corresponds to the atomic.[OpName] intrinsic. + // op(*ptr, amt) is stored to *ptr atomically. + // the return is always the original value in *ptr + ATOMIC_LOAD_AND, + ATOMIC_LOAD_OR, + ATOMIC_LOAD_XOR, + ATOMIC_LOAD_MIN, + ATOMIC_LOAD_MAX, + ATOMIC_LOAD_UMIN, + ATOMIC_LOAD_UMAX, + // BUILTIN_OP_END - This must be the last enum value in this list. BUILTIN_OP_END }; diff --git a/include/llvm/Intrinsics.td b/include/llvm/Intrinsics.td index 184e063..633063e 100644 --- a/include/llvm/Intrinsics.td +++ b/include/llvm/Intrinsics.td @@ -267,22 +267,62 @@ def int_init_trampoline : Intrinsic<[llvm_ptr_ty, llvm_ptr_ty, llvm_ptr_ty, def int_memory_barrier : Intrinsic<[llvm_void_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty, llvm_i1_ty], []>; -def int_atomic_lcs : Intrinsic<[llvm_anyint_ty, - LLVMPointerType<LLVMMatchType<0>>, - LLVMMatchType<0>, LLVMMatchType<0>], +def int_atomic_lcs : Intrinsic<[llvm_anyint_ty, + LLVMPointerType<LLVMMatchType<0>>, + LLVMMatchType<0>, LLVMMatchType<0>], + [IntrWriteArgMem]>, + GCCBuiltin<"__sync_val_compare_and_swap">; +def int_atomic_las : Intrinsic<[llvm_anyint_ty, + LLVMPointerType<LLVMMatchType<0>>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, + GCCBuiltin<"__sync_fetch_and_add">; +def int_atomic_swap : Intrinsic<[llvm_anyint_ty, + LLVMPointerType<LLVMMatchType<0>>, + LLVMMatchType<0>], [IntrWriteArgMem]>, - GCCBuiltin<"__sync_val_compare_and_swap">; -def int_atomic_las : Intrinsic<[llvm_anyint_ty, - LLVMPointerType<LLVMMatchType<0>>, - LLVMMatchType<0>], - [IntrWriteArgMem]>, - GCCBuiltin<"__sync_fetch_and_add">; -def int_atomic_swap : Intrinsic<[llvm_anyint_ty, - LLVMPointerType<LLVMMatchType<0>>, - LLVMMatchType<0>], - [IntrWriteArgMem]>, - GCCBuiltin<"__sync_lock_test_and_set">; - + GCCBuiltin<"__sync_lock_test_and_set">; +def int_atomic_lss : Intrinsic<[llvm_anyint_ty, + LLVMPointerType<LLVMMatchType<0>>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, + GCCBuiltin<"__sync_fetch_and_sub">; +def int_atomic_load_and : Intrinsic<[llvm_anyint_ty, + LLVMPointerType<LLVMMatchType<0>>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, + GCCBuiltin<"__sync_fetch_and_and">; +def int_atomic_load_or : Intrinsic<[llvm_anyint_ty, + LLVMPointerType<LLVMMatchType<0>>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, + GCCBuiltin<"__sync_fetch_and_or">; +def int_atomic_load_xor : Intrinsic<[llvm_anyint_ty, + LLVMPointerType<LLVMMatchType<0>>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, + GCCBuiltin<"__sync_fetch_and_xor">; +def int_atomic_load_min : Intrinsic<[llvm_anyint_ty, + LLVMPointerType<LLVMMatchType<0>>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, + GCCBuiltin<"__sync_fetch_and_min">; +def int_atomic_load_max : Intrinsic<[llvm_anyint_ty, + LLVMPointerType<LLVMMatchType<0>>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, + GCCBuiltin<"__sync_fetch_and_max">; +def int_atomic_load_umin : Intrinsic<[llvm_anyint_ty, + LLVMPointerType<LLVMMatchType<0>>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, + GCCBuiltin<"__sync_fetch_and_umin">; +def int_atomic_load_umax : Intrinsic<[llvm_anyint_ty, + LLVMPointerType<LLVMMatchType<0>>, + LLVMMatchType<0>], + [IntrWriteArgMem]>, + GCCBuiltin<"__sync_fetch_and_umax">; + //===-------------------------- Other Intrinsics --------------------------===// // def int_flt_rounds : Intrinsic<[llvm_i32_ty]>, diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 5f8c1c2..0b8dda8 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -1340,12 +1340,15 @@ private: /// by the system, this holds the same type (e.g. i32 -> i32). MVT::ValueType TransformToType[MVT::LAST_VALUETYPE]; + // Defines the capacity of the TargetLowering::OpActions table + static const int OpActionsCapacity = 173; + /// OpActions - For each operation and each value type, keep a LegalizeAction /// that indicates how instruction selection should deal with the operation. /// Most operations are Legal (aka, supported natively by the target), but /// operations that are not should be described. Note that operations on /// non-legal value types are not described here. - uint64_t OpActions[156]; + uint64_t OpActions[OpActionsCapacity]; /// LoadXActions - For each load of load extension type and each value type, /// keep a LegalizeAction that indicates how instruction selection should deal @@ -1378,7 +1381,7 @@ private: /// TargetDAGCombineArray - Targets can specify ISD nodes that they would /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), /// which sets a bit in this array. - unsigned char TargetDAGCombineArray[160/(sizeof(unsigned char)*8)]; + unsigned char TargetDAGCombineArray[168/(sizeof(unsigned char)*8)]; /// PromoteToType - For operations that must be promoted to a specific type, /// this holds the destination type. This map should be sparse, so don't hold |