Revert 72707 and 72709, for the moment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 10 insertions, 23 deletions

diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index c2f09b7..ec2d1d7 100644
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -324,14 +324,6 @@ public:
     return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
                    getRegister(Reg, N.getValueType()), N);
   }
-  // This version of getCopyToReg has the register (and its type) as an
-  // explicit output.
-  SDValue getCopyToReg(SDValue Chain, DebugLoc dl, MVT VT, unsigned Reg,
-                       SDValue N) {
-    SDVTList VTs = getVTList(MVT::Other, VT);
-    SDValue Ops[] = { Chain, getRegister(Reg, VT), N};
-    return getNode(ISD::CopyToReg, dl, VTs, Ops, 3);
-  }
 
   // This version of the getCopyToReg method takes an extra operand, which
   // indicates that there is potentially an incoming flag value (if Flag is not
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index 942c169..ad48510 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -242,11 +242,14 @@ namespace ISD {
     // remainder result.
     SDIVREM, UDIVREM,
 
+    // CARRY_FALSE - This node is used when folding other nodes,
+    // like ADDC/SUBC, which indicate the carry result is always false.
+    CARRY_FALSE,
+
     // Carry-setting nodes for multiple precision addition and subtraction.
     // These nodes take two operands of the same value type, and produce two
     // results.  The first result is the normal add or sub result, the second
-    // result is the carry flag result (type i1 or whatever it got expanded to
-    // for the target, value 0 or 1).
+    // result is the carry flag result.
     ADDC, SUBC,
 
     // Carry-using nodes for multiple precision addition and subtraction.  These
@@ -255,8 +258,7 @@ namespace ISD {
     // produce two results; the normal result of the add or sub, and the output
     // carry flag.  These nodes both read and write a carry flag to allow them
     // to them to be chained together for add and sub of arbitrarily large
-    // values.  The carry flag (input and output) has type i1 or whatever it
-    // got expanded to for the target, and has value 0 or 1.
+    // values.
     ADDE, SUBE,
 
     // RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index 4af1089..3f1cdd2 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -326,11 +326,6 @@ class InstrInfo {
   // Sparc manual specifies its instructions in the format [31..0] (big), while
   // PowerPC specifies them using the format [0..31] (little).
   bit isLittleEndianEncoding = 0;
-
-  // Targets that can support the HasI1 argument on ADDC and ADDE, rather than
-  // Flag, have this bit set.  This is transitional and should go away when all
-  // targets have been switched over.
-  bit supportsHasI1 = 0;
 }
 
 // Standard Instructions.
diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td
index 2586e65..2cd2967 100644
--- a/include/llvm/Target/TargetSelectionDAG.td
+++ b/include/llvm/Target/TargetSelectionDAG.td
@@ -216,8 +216,6 @@ def SDNPMayStore    : SDNodeProperty;   // May write to memory, sets 'mayStore'.
 def SDNPMayLoad     : SDNodeProperty;   // May read memory, sets 'mayLoad'.
 def SDNPSideEffect  : SDNodeProperty;   // Sets 'HasUnmodelledSideEffects'.
 def SDNPMemOperand  : SDNodeProperty;   // Touches memory, has assoc MemOperand
-def SDNPInI1        : SDNodeProperty;   // Read an extra I1 operand
-def SDNPOutI1       : SDNodeProperty;   // Write an extra I1 result
 
 //===----------------------------------------------------------------------===//
 // Selection DAG Node definitions.
@@ -291,13 +289,13 @@ def or         : SDNode<"ISD::OR"        , SDTIntBinOp,
 def xor        : SDNode<"ISD::XOR"       , SDTIntBinOp,
                         [SDNPCommutative, SDNPAssociative]>;
 def addc       : SDNode<"ISD::ADDC"      , SDTIntBinOp,
-                        [SDNPCommutative, SDNPOutI1]>;
+                        [SDNPCommutative, SDNPOutFlag]>;
 def adde       : SDNode<"ISD::ADDE"      , SDTIntBinOp,
-                        [SDNPCommutative, SDNPInI1, SDNPOutI1]>;
+                        [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
 def subc       : SDNode<"ISD::SUBC"      , SDTIntBinOp,
-                        [SDNPOutI1]>;
+                        [SDNPOutFlag]>;
 def sube       : SDNode<"ISD::SUBE"      , SDTIntBinOp,
-                        [SDNPInI1, SDNPOutI1]>;
+                        [SDNPOutFlag, SDNPInFlag]>;
                         
 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
 def bswap      : SDNode<"ISD::BSWAP"      , SDTIntUnaryOp>;