When scheduling a block in parts, keep track of the overall

instruction index across each part. Instruction indices are used
to make live range queries, and live ranges can extend beyond
scheduling region boundaries.

Refactor the ScheduleDAGSDNodes class some more so that it
doesn't have to worry about this additional information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64288 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 20 insertions, 25 deletions

diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index 786a5f4..38b437b 100644
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -31,7 +31,6 @@ namespace llvm {
   class MachineInstr;
   class TargetRegisterInfo;
   class ScheduleDAG;
-  class SelectionDAG;
   class SDNode;
   class TargetInstrInfo;
   class TargetInstrDesc;
@@ -426,10 +425,8 @@ namespace llvm {
 
   class ScheduleDAG {
   public:
-    SelectionDAG *DAG;                    // DAG of the current basic block
-    MachineBasicBlock *BB;                // Current basic block
-    MachineBasicBlock::iterator Begin;    // The beginning of the range to be scheduled.
-    MachineBasicBlock::iterator End;      // The end of the range to be scheduled.
+    MachineBasicBlock *BB;                // The block in which to insert instructions.
+    MachineBasicBlock::iterator InsertPos;// The position to insert instructions.
     const TargetMachine &TM;              // Target processor
     const TargetInstrInfo *TII;           // Target instruction information
     const TargetRegisterInfo *TRI;        // Target processor register info
@@ -452,12 +449,6 @@ namespace llvm {
     ///
     void viewGraph();
   
-    /// Run - perform scheduling.
-    ///
-    void Run(SelectionDAG *DAG, MachineBasicBlock *MBB,
-             MachineBasicBlock::iterator Begin,
-             MachineBasicBlock::iterator End);
-
     /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock
     /// according to the order specified in Sequence.
     ///
@@ -482,6 +473,10 @@ namespace llvm {
 #endif
 
   protected:
+    /// Run - perform scheduling.
+    ///
+    void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos);
+
     /// BuildSchedGraph - Build SUnits and set up their Preds and Succs
     /// to form the scheduling dependency graph.
     ///
diff --git a/include/llvm/CodeGen/SchedulerRegistry.h b/include/llvm/CodeGen/SchedulerRegistry.h
index b4daa05..c967bfc 100644
--- a/include/llvm/CodeGen/SchedulerRegistry.h
+++ b/include/llvm/CodeGen/SchedulerRegistry.h
@@ -26,13 +26,13 @@ namespace llvm {
 //===----------------------------------------------------------------------===//
 
 class SelectionDAGISel;
-class ScheduleDAG;
+class ScheduleDAGSDNodes;
 class SelectionDAG;
 class MachineBasicBlock;
 
 class RegisterScheduler : public MachinePassRegistryNode {
 public:
-  typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, bool);
+  typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, bool);
 
   static MachinePassRegistry Registry;
 
@@ -63,28 +63,28 @@ public:
 
 /// createBURRListDAGScheduler - This creates a bottom up register usage
 /// reduction list scheduler.
-ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
-                                        bool Fast);
+ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
+                                               bool Fast);
 
 /// createTDRRListDAGScheduler - This creates a top down register usage
 /// reduction list scheduler.
-ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
-                                        bool Fast);
+ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
+                                               bool Fast);
 
 /// createTDListDAGScheduler - This creates a top-down list scheduler with
 /// a hazard recognizer.
-ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
-                                      bool Fast);
+ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
+                                             bool Fast);
 
 /// createFastDAGScheduler - This creates a "fast" scheduler.
 ///
-ScheduleDAG *createFastDAGScheduler(SelectionDAGISel *IS,
-                                    bool Fast);
+ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
+                                           bool Fast);
 
 /// createDefaultScheduler - This creates an instruction scheduler appropriate
 /// for the target.
-ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
-                                    bool Fast);
+ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
+                                           bool Fast);
 
 } // end namespace llvm
 
diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index 468f1b7..e6bf8d7 100644
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -35,7 +35,7 @@ namespace llvm {
   class FunctionLoweringInfo;
   class ScheduleHazardRecognizer;
   class GCFunctionInfo;
-  class ScheduleDAG;
+  class ScheduleDAGSDNodes;
  
 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
 /// pattern-matching instruction selectors.
@@ -133,7 +133,7 @@ private:
   /// via the SchedulerRegistry, use it, otherwise select the
   /// one preferred by the target.
   ///
-  ScheduleDAG *CreateScheduler();
+  ScheduleDAGSDNodes *CreateScheduler();
 };
 
 }