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author | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2001-09-18 22:57:47 +0000 |
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committer | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2001-09-18 22:57:47 +0000 |
commit | 80acc6cf43af185f406cbe29b3ba902a3528717f (patch) | |
tree | b52414402dab75713f60291eb9ef25904b9ed65a /include | |
parent | eda6806f6aaec9a64707a8e5609ae21b15e1440a (diff) | |
download | external_llvm-80acc6cf43af185f406cbe29b3ba902a3528717f.zip external_llvm-80acc6cf43af185f406cbe29b3ba902a3528717f.tar.gz external_llvm-80acc6cf43af185f406cbe29b3ba902a3528717f.tar.bz2 |
*** empty log message ***
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@634 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r-- | include/llvm/Target/TargetRegInfo.h | 116 |
1 files changed, 56 insertions, 60 deletions
diff --git a/include/llvm/Target/TargetRegInfo.h b/include/llvm/Target/TargetRegInfo.h index d8c6a96..aab0980 100644 --- a/include/llvm/Target/TargetRegInfo.h +++ b/include/llvm/Target/TargetRegInfo.h @@ -62,7 +62,6 @@ public: - //--------------------------------------------------------------------------- // class MachineRegInfo // @@ -83,13 +82,12 @@ class MachineRegInfo : public NonCopyableV { protected: - MachineRegClassArrayType MachineRegClassArr; - + MachineRegClassArrayType MachineRegClassArr; + public: - MachineRegInfo() {} - + // According the definition of a MachineOperand class, a Value in a // machine instruction can go into either a normal register or a // condition code register. If isCCReg is true below, the ID of the condition @@ -99,9 +97,6 @@ public: bool isCCReg = false) const =0; - // returns the register that is hardwired to zero if any (-1 if none) - virtual inline int getZeroRegNum() const = 0; - inline unsigned int getNumOfRegClasses() const { return MachineRegClassArr.size(); } @@ -110,7 +105,8 @@ public: return MachineRegClassArr[i]; } - + // returns the register that is hardwired to zero if any (-1 if none) + virtual inline int getZeroRegNum() const = 0; //virtual unsigned getRegClassIDOfValue (const Value *const Val) const = 0; // this method must give the exact register class of a machine operand @@ -125,81 +121,76 @@ public: LiveRangeInfo& LRI, AddedInstrMapType& AddedInstrMap ) const = 0 ; + virtual void colorRetArg(vector<const Instruction *> & + RetInstrList, LiveRangeInfo& LRI, + AddedInstrMapType &AddedInstrMap) const =0; + + // returns the reg used for pushing the address when a method is called. + // This can be used for other purposes between calls + virtual unsigned getCallAddressReg() const = 0; + + // and when we return from a method. It should be made sure that this + // register contains the return value when a return instruction is reached. + virtual unsigned getReturnAddressReg() const = 0; + virtual int getUnifiedRegNum(int RegClassID, int reg) const = 0; virtual const string getUnifiedRegName(int UnifiedRegNum) const = 0; //virtual void printReg(const LiveRange *const LR) const =0; + + MachineRegInfo() { } + }; +#endif #if 0 -class Value; -class Instruction; -class Method; -class LiveRangeInfo; -class LiveRange; -class AddedInstrns; -class MachineInstr; - -//----------------------------------------------------------------------------- -// class MachineRegClassInfo +//--------------------------------------------------------------------------- +// class MachineRegInfo // // Purpose: -// Interface to description of machine register class (e.g., int reg class -// float reg class etc) +// Interface to register info of target machine // //-------------------------------------------------------------------------- -class IGNode; -class MachineRegClassInfo { -protected: - const unsigned RegClassID; // integer ID of a reg class - const unsigned NumOfAvailRegs; // # of avail for coloring -without SP etc. - const unsigned NumOfAllRegs; // # of all registers -including SP,g0 etc. -public: - - inline unsigned getRegClassID() const { return RegClassID; } - inline unsigned getNumOfAvailRegs() const { return NumOfAvailRegs; } - inline unsigned getNumOfAllRegs() const { return NumOfAllRegs; } +typedef hash_map<const MachineInstr *, AddedInstrns *> AddedInstrMapType; +// A vector of all machine register classes +typedef vector<const MachineRegClassInfo *> MachineRegClassArrayType; - // This method should find a color which is not used by neighbors - // (i.e., a false position in IsColorUsedArr) and - virtual void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const = 0; +class MachineRegInfo : public NonCopyableV { - MachineRegClassInfo(const unsigned ID, const unsigned NVR, - const unsigned NAR): RegClassID(ID), NumOfAvailRegs(NVR), - NumOfAllRegs(NAR) { } -}; +protected: -//--------------------------------------------------------------------------- -// class MachineRegInfo -// -// Purpose: -// Interface to register info of target machine -// -//-------------------------------------------------------------------------- + MachineRegClassArrayType MachineRegClassArr; -typedef hash_map<const MachineInstr *, AddedInstrns *> AddedInstrMapType; -// A vector of all machine register classestypedef vector<const MachineRegClassInfo *> MachineRegClassArrayType; +public: + MachineRegInfo() {} + + // According the definition of a MachineOperand class, a Value in a + // machine instruction can go into either a normal register or a + // condition code register. If isCCReg is true below, the ID of the condition + // code regiter class will be returned. Otherwise, the normal register + // class (eg. int, float) must be returned. + virtual unsigned getRegClassIDOfValue (const Value *const Val, + bool isCCReg = false) const =0; -class MachineRegInfo : public NonCopyableV { -protected: - MachineRegClassArrayType MachineRegClassArr; - -public: + + // returns the register that is hardwired to zero if any (-1 if none) + virtual inline int getZeroRegNum() const = 0; + inline unsigned int getNumOfRegClasses() const { return MachineRegClassArr.size(); } @@ -209,27 +200,32 @@ public: } - virtual unsigned getRegClassIDOfValue (const Value *const Val) const = 0; + + //virtual unsigned getRegClassIDOfValue (const Value *const Val) const = 0; + // this method must give the exact register class of a machine operand + // e.g, Int, Float, Int CC, Float CC + //virtual unsigned getRCIDOfMachineOp (const MachineOperand &MO) const = 0; + virtual void colorArgs(const Method *const Meth, LiveRangeInfo & LRI) const = 0; virtual void colorCallArgs(vector<const Instruction *> & CallInstrList, LiveRangeInfo& LRI, - AddedInstrMapType& AddedInstrMap ) const = 0; + AddedInstrMapType& AddedInstrMap ) const = 0 ; virtual int getUnifiedRegNum(int RegClassID, int reg) const = 0; - virtual const string getUnifiedRegName(int reg) const = 0; + virtual const string getUnifiedRegName(int UnifiedRegNum) const = 0; //virtual void printReg(const LiveRange *const LR) const =0; - - MachineRegInfo() { } - }; + #endif -#endif + + + |