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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-10-10 18:47:35 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-10-10 18:47:35 +0000 |
| commit | 89dedc1b65cb09a652d251273e2eae938dead60b (patch) | |
| tree | 3cd1610c5bfb746ae7b1a8511bba796c643eb903 /include | |
| parent | b8e48a636e7ee6c13140382eb93d9695a65b0624 (diff) | |
| download | external_llvm-89dedc1b65cb09a652d251273e2eae938dead60b.zip external_llvm-89dedc1b65cb09a652d251273e2eae938dead60b.tar.gz external_llvm-89dedc1b65cb09a652d251273e2eae938dead60b.tar.bz2 | |
Fix grammar / missing words
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192380 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
| -rw-r--r-- | include/llvm/Target/TargetOpcodes.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/include/llvm/Target/TargetOpcodes.h b/include/llvm/Target/TargetOpcodes.h index 516e070..86ac7df 100644 --- a/include/llvm/Target/TargetOpcodes.h +++ b/include/llvm/Target/TargetOpcodes.h @@ -69,8 +69,9 @@ namespace TargetOpcode { DBG_VALUE = 11, /// REG_SEQUENCE - This variadic instruction is used to form a register that - /// represent a consecutive sequence of sub-registers. It's used as register - /// coalescing / allocation aid and must be eliminated before code emission. + /// represents a consecutive sequence of sub-registers. It's used as a + /// register coalescing / allocation aid and must be eliminated before code + /// emission. // In SDNode form, the first operand encodes the register class created by // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index // pair. Once it has been lowered to a MachineInstr, the regclass operand |