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authorAndrew Lenharth <andrewl@lenharth.org>2005-11-11 22:48:54 +0000
committerAndrew Lenharth <andrewl@lenharth.org>2005-11-11 22:48:54 +0000
commit8b91c77385a055474d271aa8c10f0382fdeaafeb (patch)
tree10b6779a9d1d0e5670a3eb63a11f3c6e9b07174b /include
parentc2c64fd3c632df179269db9c80b2d7f071115d2c (diff)
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added a chain output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24306 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r--include/llvm/CodeGen/SelectionDAGNodes.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index 94ef5d5..3af9008 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -308,6 +308,9 @@ namespace ISD {
PCMARKER,
// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
+ // The only operand is a chain and a value and a chain are produced. The
+ // value is the contents of the architecture specific cycle counter like
+ // register (or other high accuracy low latency clock source)
READCYCLECOUNTER,
// READPORT, WRITEPORT, READIO, WRITEIO - These correspond to the LLVM