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author | Evan Cheng <evan.cheng@apple.com> | 2010-09-30 22:01:50 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2010-09-30 22:01:50 +0000 |
commit | a56927e3ffed66007b4f9d095ff4425425452a15 (patch) | |
tree | c2581f03c41843fa8e81c631fa4cc61d66273e19 /include | |
parent | c6877b4ee11e1937b185114680a983facf9a29f8 (diff) | |
download | external_llvm-a56927e3ffed66007b4f9d095ff4425425452a15.zip external_llvm-a56927e3ffed66007b4f9d095ff4425425452a15.tar.gz external_llvm-a56927e3ffed66007b4f9d095ff4425425452a15.tar.bz2 |
Comments about operand cycles and pipeline forwarding pathes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115214 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r-- | include/llvm/Target/TargetSchedule.td | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/include/llvm/Target/TargetSchedule.td b/include/llvm/Target/TargetSchedule.td index c55ebd8..97ea82a 100644 --- a/include/llvm/Target/TargetSchedule.td +++ b/include/llvm/Target/TargetSchedule.td @@ -27,7 +27,6 @@ class FuncUnit; // pipeline bypasses which can be used to forward results of instructions // that are forwarded to uses. class Bypass; - def NoBypass : Bypass; class ReservationKind<bits<1> val> { @@ -88,6 +87,23 @@ def NoItinerary : InstrItinClass; // Instruction itinerary data - These values provide a runtime map of an // instruction itinerary class (name) to its itinerary data. // +// OperandCycles are optional "cycle counts". They specify the cycle after +// instruction issue the values which correspond to specific operand indices +// are defined or read. Bypasses are optional "pipeline forwarding pathes", if +// a def by an instruction is available on a specific bypass and the use can +// read from the same bypass, then the operand use latency is reduced by one. +// +// InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Pipe1]>, +// InstrStage<1, [A9_AGU]>], +// [3, 1], [A9_LdBypass]>, +// InstrItinData<IIC_iMVNr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], +// [1, 1], [NoBypass, A9_LdBypass]>, +// +// In this example, the instruction of IIC_iLoadi reads its input on cycle 1 +// (after issue) and the result of the load is available on cycle 3. The result +// is available via forwarding path A9_LdBypass. If it's used by the first +// source operand of instructions of IIC_iMVNr class, then the operand latency +// is reduced by 1. class InstrItinData<InstrItinClass Class, list<InstrStage> stages, list<int> operandcycles = [], list<Bypass> bypasses = []> { |