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authorHal Finkel <hfinkel@anl.gov>2013-03-26 21:20:15 +0000
committerHal Finkel <hfinkel@anl.gov>2013-03-26 21:20:15 +0000
commitdf23a60fa6ce053511388e1bccca5900757e1aac (patch)
tree04bc845a8f51f567e5785cc7d8a5c55ec81810e0 /include
parentaa6047d23d8ed55abd8545f5cbe82cd13cbd756a (diff)
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Fix the register scavenger for targets that provide custom spilling
As pointed out by Richard Sandiford, my recent updates to the register scavenger broke targets that use custom spilling (because the new code assumed that if there were no valid spill slots, than spilling would be impossible). I don't have a test case, but it should be possible to create one for Thumb 1, Mips 16, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178073 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r--include/llvm/CodeGen/RegisterScavenging.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/include/llvm/CodeGen/RegisterScavenging.h b/include/llvm/CodeGen/RegisterScavenging.h
index 0eb2b2a..49d1689 100644
--- a/include/llvm/CodeGen/RegisterScavenging.h
+++ b/include/llvm/CodeGen/RegisterScavenging.h
@@ -42,7 +42,7 @@ class RegScavenger {
/// Information on scavenged registers (held in a spill slot).
struct ScavengedInfo {
- ScavengedInfo(int FI) : FrameIndex(FI), Reg(0), Restore(NULL) {}
+ ScavengedInfo(int FI = -1) : FrameIndex(FI), Reg(0), Restore(NULL) {}
/// A spill slot used for scavenging a register post register allocation.
int FrameIndex;
@@ -130,7 +130,8 @@ public:
void getScavengingFrameIndices(SmallVectorImpl<int> &A) const {
for (SmallVector<ScavengedInfo, 2>::const_iterator I = Scavenged.begin(),
IE = Scavenged.end(); I != IE; ++I)
- A.push_back(I->FrameIndex);
+ if (I->FrameIndex >= 0)
+ A.push_back(I->FrameIndex);
}
/// scavengeRegister - Make a register of the specific register class