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authorDale Johannesen <dalej@apple.com>2007-09-23 14:52:20 +0000
committerDale Johannesen <dalej@apple.com>2007-09-23 14:52:20 +0000
commitf1fc3a8fa6d4e81e30c08983d786c640acb2591c (patch)
tree309842454fb97a870e0b66d8dc70bfa9ef9b17b7 /include
parentab4456f10a72f3a7c73dac0e95578b9b7e4250b8 (diff)
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Fix PR 1681. When X86 target uses +sse -sse2,
keep f32 in SSE registers and f64 in x87. This is effectively a new codegen mode. Change addLegalFPImmediate to permit float and double variants to do different things. Adjust callers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42246 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r--include/llvm/Target/TargetLowering.h10
1 files changed, 0 insertions, 10 deletions
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 88b3823..8586d7f 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -783,17 +783,7 @@ protected:
/// addLegalFPImmediate - Indicate that this target can instruction select
/// the specified FP immediate natively.
void addLegalFPImmediate(const APFloat& Imm) {
- // Incoming constants are expected to be double. We also add
- // the float version. It is expected that all constants are exactly
- // representable as floats.
- assert(&Imm.getSemantics() == &APFloat::IEEEdouble);
- APFloat Immf = APFloat(Imm);
- // Rounding mode is not supposed to matter here...
- if (Immf.convert(APFloat::IEEEsingle, APFloat::rmNearestTiesToEven) !=
- APFloat::opOK)
- assert(0);
LegalFPImmediates.push_back(Imm);
- LegalFPImmediates.push_back(Immf);
}
/// setTargetDAGCombine - Targets should invoke this method for each target