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authorAdrian Prantl <aprantl@apple.com>2013-07-09 20:28:37 +0000
committerAdrian Prantl <aprantl@apple.com>2013-07-09 20:28:37 +0000
commit3517640443f0b5224e2a6414c246ac60016ee9d4 (patch)
tree011ad059026ee96743b0327cd32e41679c4f4021 /lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
parent7d185e4e5b1da7e07e1c3b9539e2c9bc8e983e62 (diff)
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Reapply an improved version of r180816/180817.
Change the informal convention of DBG_VALUE machine instructions so that we can express a register-indirect address with an offset of 0. The old convention was that a DBG_VALUE is a register-indirect value if the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE is register-indirect if the first operand is a register and the second operand is an immediate. For plain register values the combination reg, reg is used. MachineInstrBuilder::BuildMI knows how to build the new DBG_VALUES. rdar://problem/13658587 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185966 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp')
-rw-r--r--lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp b/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
index ec7c5bf..3e6db1c 100644
--- a/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
+++ b/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
@@ -1563,8 +1563,9 @@ DIE *CompileUnit::constructVariableDIE(DbgVariable *DV,
assert(DVInsn->getNumOperands() == 3);
if (DVInsn->getOperand(0).isReg()) {
const MachineOperand RegOp = DVInsn->getOperand(0);
- if (int64_t Offset = DVInsn->getOperand(1).getImm()) {
- MachineLocation Location(RegOp.getReg(), Offset);
+ // If the second operand is an immedieate, this is an indirect value.
+ if (DVInsn->getOperand(1).isImm()) {
+ MachineLocation Location(RegOp.getReg(), DVInsn->getOperand(1).getImm());
addVariableAddress(*DV, VariableDie, Location);
} else if (RegOp.getReg())
addVariableAddress(*DV, VariableDie, MachineLocation(RegOp.getReg()));