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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-03-29 21:20:19 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-03-29 21:20:19 +0000 |
commit | 6094bd87d845afabba5b99ec4848fa6116bac682 (patch) | |
tree | 16e0d4e352d6c8446a6e31a831d3740fd0570808 /lib/CodeGen/InlineSpiller.cpp | |
parent | 3d090558510de9a3601965630c5c82d663c346ce (diff) | |
download | external_llvm-6094bd87d845afabba5b99ec4848fa6116bac682.zip external_llvm-6094bd87d845afabba5b99ec4848fa6116bac682.tar.gz external_llvm-6094bd87d845afabba5b99ec4848fa6116bac682.tar.bz2 |
Recompute register class and hint for registers created during spilling.
The spill weight is not recomputed for an unspillable register - it stays infinite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128490 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/InlineSpiller.cpp')
-rw-r--r-- | lib/CodeGen/InlineSpiller.cpp | 74 |
1 files changed, 41 insertions, 33 deletions
diff --git a/lib/CodeGen/InlineSpiller.cpp b/lib/CodeGen/InlineSpiller.cpp index 397943b..d0c7507 100644 --- a/lib/CodeGen/InlineSpiller.cpp +++ b/lib/CodeGen/InlineSpiller.cpp @@ -139,6 +139,7 @@ private: MachineBasicBlock::iterator MI); void spillAroundUses(unsigned Reg); + void spillAll(); }; } @@ -629,10 +630,6 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, LiveInterval &NewLI = Edit->createFrom(VirtReg.reg, LIS, VRM); NewLI.markNotSpillable(); - // Rematting for a copy: Set allocation hint to be the destination register. - if (MI->isCopy()) - MRI.setRegAllocationHint(NewLI.reg, 0, MI->getOperand(0).getReg()); - // Finally we can rematerialize OrigMI before MI. SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM, LIS, TII, TRI); @@ -718,6 +715,11 @@ void InlineSpiller::reMaterializeAll() { DEBUG(dbgs() << RegsToSpill.size() << " registers to spill after remat.\n"); } + +//===----------------------------------------------------------------------===// +// Spilling +//===----------------------------------------------------------------------===// + /// If MI is a load or store of StackSlot, it can be removed. bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) { int FI = 0; @@ -906,31 +908,8 @@ void InlineSpiller::spillAroundUses(unsigned Reg) { } } -void InlineSpiller::spill(LiveRangeEdit &edit) { - Edit = &edit; - assert(!TargetRegisterInfo::isStackSlot(edit.getReg()) - && "Trying to spill a stack slot."); - // Share a stack slot among all descendants of Original. - Original = VRM.getOriginal(edit.getReg()); - StackSlot = VRM.getStackSlot(Original); - StackInt = 0; - - DEBUG(dbgs() << "Inline spilling " - << MRI.getRegClass(edit.getReg())->getName() - << ':' << edit.getParent() << "\nFrom original " - << LIS.getInterval(Original) << '\n'); - assert(edit.getParent().isSpillable() && - "Attempting to spill already spilled value."); - assert(DeadDefs.empty() && "Previous spill didn't remove dead defs"); - - collectRegsToSpill(); - analyzeSiblingValues(); - reMaterializeAll(); - - // Remat may handle everything. - if (RegsToSpill.empty()) - return; - +/// spillAll - Spill all registers remaining after rematerialization. +void InlineSpiller::spillAll() { // Update LiveStacks now that we are committed to spilling. if (StackSlot == VirtRegMap::NO_STACK_SLOT) { StackSlot = VRM.assignVirt2StackSlot(Original); @@ -939,8 +918,8 @@ void InlineSpiller::spill(LiveRangeEdit &edit) { } else StackInt = &LSS.getInterval(StackSlot); - if (Original != edit.getReg()) - VRM.assignVirt2StackSlot(edit.getReg(), StackSlot); + if (Original != Edit->getReg()) + VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot); assert(StackInt->getNumValNums() == 1 && "Bad stack interval values"); for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) @@ -959,7 +938,7 @@ void InlineSpiller::spill(LiveRangeEdit &edit) { } // Finally delete the SnippetCopies. - for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(edit.getReg()); + for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()); MachineInstr *MI = RI.skipInstruction();) { assert(SnippetCopies.count(MI) && "Remaining use wasn't a snippet copy"); // FIXME: Do this with a LiveRangeEdit callback. @@ -968,6 +947,35 @@ void InlineSpiller::spill(LiveRangeEdit &edit) { MI->eraseFromParent(); } + // Delete all spilled registers. for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) - edit.eraseVirtReg(RegsToSpill[i], LIS); + Edit->eraseVirtReg(RegsToSpill[i], LIS); +} + +void InlineSpiller::spill(LiveRangeEdit &edit) { + Edit = &edit; + assert(!TargetRegisterInfo::isStackSlot(edit.getReg()) + && "Trying to spill a stack slot."); + // Share a stack slot among all descendants of Original. + Original = VRM.getOriginal(edit.getReg()); + StackSlot = VRM.getStackSlot(Original); + StackInt = 0; + + DEBUG(dbgs() << "Inline spilling " + << MRI.getRegClass(edit.getReg())->getName() + << ':' << edit.getParent() << "\nFrom original " + << LIS.getInterval(Original) << '\n'); + assert(edit.getParent().isSpillable() && + "Attempting to spill already spilled value."); + assert(DeadDefs.empty() && "Previous spill didn't remove dead defs"); + + collectRegsToSpill(); + analyzeSiblingValues(); + reMaterializeAll(); + + // Remat may handle everything. + if (!RegsToSpill.empty()) + spillAll(); + + Edit->calculateRegClassAndHint(MF, LIS, Loops); } |