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| author | Andrew Trick <atrick@apple.com> | 2012-02-22 06:08:11 +0000 |
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| committer | Andrew Trick <atrick@apple.com> | 2012-02-22 06:08:11 +0000 |
| commit | b4566a999970b514d7c6973d99e293a6625d3f70 (patch) | |
| tree | e1dab12fabb7e460c56467210a23c15d87138e2f /lib/CodeGen/IntrinsicLowering.cpp | |
| parent | 44d23825d61d530b8d562329ec8fc2d4f843bb8d (diff) | |
| download | external_llvm-b4566a999970b514d7c6973d99e293a6625d3f70.zip external_llvm-b4566a999970b514d7c6973d99e293a6625d3f70.tar.gz external_llvm-b4566a999970b514d7c6973d99e293a6625d3f70.tar.bz2 | |
Initialize SUnits before DAG building.
Affect on SD scheduling and postRA scheduling:
Printing the DAG will display the nodes in top-down topological order.
This matches the order within the MBB and makes my life much easier in general.
Affect on misched:
We don't need to track virtual register uses at all. This is awesome.
I also intend to rely on the SUnit ID as a topo-sort index. So if A < B then we cannot have an edge B -> A.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151135 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/IntrinsicLowering.cpp')
0 files changed, 0 insertions, 0 deletions