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author | Bill Wendling <isanbard@gmail.com> | 2009-08-22 20:23:49 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2009-08-22 20:23:49 +0000 |
commit | 0d6b1b124888e568b4dd2037a9e31dcd54e62d18 (patch) | |
tree | 1a7f8b288e1881027547351210d653d1197738ed /lib/CodeGen/LowerSubregs.cpp | |
parent | 8e6179fb134af929ee7c937c82d9dc1c9a104c5f (diff) | |
download | external_llvm-0d6b1b124888e568b4dd2037a9e31dcd54e62d18.zip external_llvm-0d6b1b124888e568b4dd2037a9e31dcd54e62d18.tar.gz external_llvm-0d6b1b124888e568b4dd2037a9e31dcd54e62d18.tar.bz2 |
Convert DOUT to DEBUG(errs()...).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79753 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/LowerSubregs.cpp')
-rw-r--r-- | lib/CodeGen/LowerSubregs.cpp | 57 |
1 files changed, 27 insertions, 30 deletions
diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp index f34b290..812d97d 100644 --- a/lib/CodeGen/LowerSubregs.cpp +++ b/lib/CodeGen/LowerSubregs.cpp @@ -121,7 +121,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { "Extract destination must be in a physical register"); assert(SrcReg && "invalid subregister index for register"); - DOUT << "subreg: CONVERTING: " << *MI; + DEBUG(errs() << "subreg: CONVERTING: " << *MI); if (SrcReg == DstReg) { // No need to insert an identity copy instruction. @@ -130,10 +130,11 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { // instruction with IMPLICIT_DEF. MI->setDesc(TII.get(TargetInstrInfo::IMPLICIT_DEF)); MI->RemoveOperand(2); // SubIdx - DOUT << "subreg: replace by: " << *MI; + DEBUG(errs() << "subreg: replace by: " << *MI); return true; } - DOUT << "subreg: eliminated!"; + + DEBUG(errs() << "subreg: eliminated!"); } else { // Insert copy const TargetRegisterClass *TRCS = TRI.getPhysicalRegisterRegClass(DstReg); @@ -146,14 +147,13 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { TransferDeadFlag(MI, DstReg, TRI); if (MI->getOperand(1).isKill()) TransferKillFlag(MI, SuperReg, TRI, true); - -#ifndef NDEBUG - MachineBasicBlock::iterator dMI = MI; - DOUT << "subreg: " << *(--dMI); -#endif + DEBUG({ + MachineBasicBlock::iterator dMI = MI; + errs() << "subreg: " << *(--dMI); + }); } - DOUT << "\n"; + DEBUG(errs() << '\n'); MBB->erase(MI); return true; } @@ -181,7 +181,7 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) { assert(TargetRegisterInfo::isPhysicalRegister(InsReg) && "Inserted value must be in a physical register"); - DOUT << "subreg: CONVERTING: " << *MI; + DEBUG(errs() << "subreg: CONVERTING: " << *MI); if (DstSubReg == InsReg && InsSIdx == 0) { // No need to insert an identify copy instruction. @@ -190,7 +190,7 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) { // %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3 // The first def is defining RAX, not EAX so the top bits were not // zero extended. - DOUT << "subreg: eliminated!"; + DEBUG(errs() << "subreg: eliminated!"); } else { // Insert sub-register copy const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg); @@ -201,14 +201,13 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) { TransferDeadFlag(MI, DstSubReg, TRI); if (MI->getOperand(2).isKill()) TransferKillFlag(MI, InsReg, TRI); - -#ifndef NDEBUG - MachineBasicBlock::iterator dMI = MI; - DOUT << "subreg: " << *(--dMI); -#endif + DEBUG({ + MachineBasicBlock::iterator dMI = MI; + errs() << "subreg: " << *(--dMI); + }); } - DOUT << "\n"; + DEBUG(errs() << '\n'); MBB->erase(MI); return true; } @@ -239,7 +238,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { assert(TargetRegisterInfo::isPhysicalRegister(InsReg) && "Inserted value must be in a physical register"); - DOUT << "subreg: CONVERTING: " << *MI; + DEBUG(errs() << "subreg: CONVERTING: " << *MI); if (DstSubReg == InsReg) { // No need to insert an identity copy instruction. If the SrcReg was @@ -252,7 +251,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { else MIB.addReg(InsReg, RegState::ImplicitKill); } else { - DOUT << "subreg: eliminated!\n"; + DEBUG(errs() << "subreg: eliminated!\n"); MBB->erase(MI); return true; } @@ -287,12 +286,11 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { TransferKillFlag(MI, InsReg, TRI); } -#ifndef NDEBUG - MachineBasicBlock::iterator dMI = MI; - DOUT << "subreg: " << *(--dMI); -#endif + DEBUG({ + MachineBasicBlock::iterator dMI = MI; + errs() << "subreg: " << *(--dMI) << "\n"; + }); - DOUT << "\n"; MBB->erase(MI); return true; } @@ -301,13 +299,12 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { /// copies. /// bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) { - DOUT << "Machine Function\n"; - - bool MadeChange = false; + DEBUG(errs() << "Machine Function\n" + << "********** LOWERING SUBREG INSTRS **********\n" + << "********** Function: " + << MF.getFunction()->getName() << '\n'); - DOUT << "********** LOWERING SUBREG INSTRS **********\n"; - DEBUG(errs() << "********** Function: " - << MF.getFunction()->getName() << '\n'); + bool MadeChange = false; for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end(); mbbi != mbbe; ++mbbi) { |