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| author | Dan Gohman <gohman@apple.com> | 2009-01-13 20:24:13 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-01-13 20:24:13 +0000 |
| commit | 0f0e2c84f9e1202d5a9fad1cc18f75d3fd661003 (patch) | |
| tree | ca0c8659323b4d12946471be758a50bbd2d96735 /lib/CodeGen/MachineModuleInfo.cpp | |
| parent | 28e78f033533058f1834cba526de20b46ff58894 (diff) | |
| download | external_llvm-0f0e2c84f9e1202d5a9fad1cc18f75d3fd661003.zip external_llvm-0f0e2c84f9e1202d5a9fad1cc18f75d3fd661003.tar.gz external_llvm-0f0e2c84f9e1202d5a9fad1cc18f75d3fd661003.tar.bz2 | |
The list-td and list-tdrr schedulers don't yet support physreg
scheduling dependencies. Add assertion checks to help catch
this.
It appears the Mips target defaults to list-td, and it has a
regression test that uses a physreg dependence. Such code was
liable to be miscompiled, and now evokes an assertion failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62177 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineModuleInfo.cpp')
0 files changed, 0 insertions, 0 deletions