aboutsummaryrefslogtreecommitdiffstats
path: root/lib/CodeGen/MachineRegisterInfo.cpp
diff options
context:
space:
mode:
authorJakob Stoklund Olesen <stoklund@2pi.dk>2011-08-09 16:46:27 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2011-08-09 16:46:27 +0000
commit6d1fd0b979cb88809ebb77a24f4da69e1d67606b (patch)
treeca8e4a42c2abc216b48849a0adff87ea35349d6c /lib/CodeGen/MachineRegisterInfo.cpp
parent719927a68f5b8ca34bacbeb7c970f281e27cbf63 (diff)
downloadexternal_llvm-6d1fd0b979cb88809ebb77a24f4da69e1d67606b.zip
external_llvm-6d1fd0b979cb88809ebb77a24f4da69e1d67606b.tar.gz
external_llvm-6d1fd0b979cb88809ebb77a24f4da69e1d67606b.tar.bz2
Move CalculateRegClass to MRI::recomputeRegClass.
This function doesn't have anything to do with spill weights, and MRI already has functions for manipulating the register class of a virtual register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137123 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineRegisterInfo.cpp')
-rw-r--r--lib/CodeGen/MachineRegisterInfo.cpp33
1 files changed, 32 insertions, 1 deletions
diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp
index 62dd576..d795389 100644
--- a/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/lib/CodeGen/MachineRegisterInfo.cpp
@@ -14,7 +14,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Support/CommandLine.h"
+#include "llvm/Target/TargetMachine.h"
using namespace llvm;
MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI)
@@ -61,6 +61,37 @@ MachineRegisterInfo::constrainRegClass(unsigned Reg,
return NewRC;
}
+bool
+MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
+ const TargetInstrInfo *TII = TM.getInstrInfo();
+ const TargetRegisterInfo *TRI = TM.getRegisterInfo();
+ const TargetRegisterClass *OldRC = getRegClass(Reg);
+ const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
+
+ // Stop early if there is no room to grow.
+ if (NewRC == OldRC)
+ return false;
+
+ // Accumulate constraints from all uses.
+ for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
+ ++I) {
+ // TRI doesn't have accurate enough information to model this yet.
+ if (I.getOperand().getSubReg())
+ return false;
+ // Inline asm instuctions don't remember their constraints.
+ if (I->isInlineAsm())
+ return false;
+ const TargetRegisterClass *OpRC =
+ TII->getRegClass(I->getDesc(), I.getOperandNo(), TRI);
+ if (OpRC)
+ NewRC = getCommonSubClass(NewRC, OpRC);
+ if (!NewRC || NewRC == OldRC)
+ return false;
+ }
+ setRegClass(Reg, NewRC);
+ return true;
+}
+
/// createVirtualRegister - Create and return a new virtual register in the
/// function with the specified register class.
///