Remove final verification in RABasic.

We now have a proper machine code verifier pass between register
allocation and rewriting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158577 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 0 insertions, 20 deletions

diff --git a/lib/CodeGen/RegAllocBasic.cpp b/lib/CodeGen/RegAllocBasic.cpp
index 6d06480..1fa54cd 100644
--- a/lib/CodeGen/RegAllocBasic.cpp
+++ b/lib/CodeGen/RegAllocBasic.cpp
@@ -314,26 +314,6 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
   // optional HTML output
   DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM));
 
-  // FIXME: Verification currently must run before VirtRegRewriter. We should
-  // make the rewriter a separate pass and override verifyAnalysis instead. When
-  // that happens, verification naturally falls under VerifyMachineCode.
-#ifndef NDEBUG
-  if (VerifyEnabled) {
-    // Verify accuracy of LiveIntervals. The standard machine code verifier
-    // ensures that each LiveIntervals covers all uses of the virtual reg.
-
-    // FIXME: MachineVerifier is badly broken when using the standard
-    // spiller. Always use -spiller=inline with -verify-regalloc. Even with the
-    // inline spiller, some tests fail to verify because the coalescer does not
-    // always generate verifiable code.
-    MF->verify(this, "In RABasic::verify");
-
-    // Verify that LiveIntervals are partitioned into unions and disjoint within
-    // the unions.
-    verify();
-  }
-#endif // !NDEBUG
-
   releaseMemory();
   return true;
 }