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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-07-14 00:31:14 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-07-14 00:31:14 +0000 |
commit | 6a9feaac935c9345f825b272cf3225248e282f3f (patch) | |
tree | 3dea0c08b277f98940c0512fa9c95bc77a20f5c3 /lib/CodeGen/RegAllocGreedy.cpp | |
parent | 7e9450107148895cd882dbaa21f17727b876998a (diff) | |
download | external_llvm-6a9feaac935c9345f825b272cf3225248e282f3f.zip external_llvm-6a9feaac935c9345f825b272cf3225248e282f3f.tar.gz external_llvm-6a9feaac935c9345f825b272cf3225248e282f3f.tar.bz2 |
Count references to interference cache entries.
Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.
This makes it possible to have multiple live cursors examining
interference for different physregs.
The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().
Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135121 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocGreedy.cpp')
-rw-r--r-- | lib/CodeGen/RegAllocGreedy.cpp | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp index 4728a05..8677a3e 100644 --- a/lib/CodeGen/RegAllocGreedy.cpp +++ b/lib/CodeGen/RegAllocGreedy.cpp @@ -854,11 +854,6 @@ void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, }); InterferenceCache::Cursor &Intf = Cand.Intf; - - // FIXME: We need cache reference counts to guarantee that Intf hasn't been - // clobbered. - Intf.setPhysReg(IntfCache, Cand.PhysReg); - LiveRangeEdit LREdit(VirtReg, NewVRegs, this); SE->reset(LREdit); @@ -1252,6 +1247,22 @@ unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, Order.rewind(); while (unsigned PhysReg = Order.next()) { + // Discard bad candidates before we run out of interference cache cursors. + // This will only affect register classes with a lot of registers (>32). + if (NumCands == IntfCache.getMaxCursors()) { + unsigned WorstCount = ~0u; + unsigned Worst = 0; + for (unsigned i = 0; i != NumCands; ++i) { + if (i == BestCand) + continue; + unsigned Count = GlobalCand[i].LiveBundles.count(); + if (Count < WorstCount) + Worst = i, WorstCount = Count; + } + --NumCands; + GlobalCand[Worst] = GlobalCand[NumCands]; + } + if (GlobalCand.size() <= NumCands) GlobalCand.resize(NumCands+1); GlobalSplitCandidate &Cand = GlobalCand[NumCands]; |