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author | Anton Korobeynikov <asl@math.spbu.ru> | 2008-02-20 12:07:57 +0000 |
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committer | Anton Korobeynikov <asl@math.spbu.ru> | 2008-02-20 12:07:57 +0000 |
commit | 4aefd6b7d4dadf8109221a89742725c116d8f8e0 (patch) | |
tree | b6cea47a8fde646984abfe138325ccc046923420 /lib/CodeGen/RegAllocLinearScan.cpp | |
parent | 44a2a79f1865807cf976932fac00648f60edfdbe (diff) | |
download | external_llvm-4aefd6b7d4dadf8109221a89742725c116d8f8e0.zip external_llvm-4aefd6b7d4dadf8109221a89742725c116d8f8e0.tar.gz external_llvm-4aefd6b7d4dadf8109221a89742725c116d8f8e0.tar.bz2 |
Fix newly-introduced 4.3 warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47375 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocLinearScan.cpp')
-rw-r--r-- | lib/CodeGen/RegAllocLinearScan.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index c70ff95..f4f994c 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -224,11 +224,12 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) { unsigned SrcReg, DstReg; if (!CopyMI || !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) return Reg; - if (TargetRegisterInfo::isVirtualRegister(SrcReg)) + if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { if (!vrm_->isAssignedReg(SrcReg)) return Reg; else SrcReg = vrm_->getPhys(SrcReg); + } if (Reg == SrcReg) return Reg; @@ -864,7 +865,7 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) { // If copy coalescer has assigned a "preferred" register, check if it's // available first. - if (cur->preference) + if (cur->preference) { if (prt_->isRegAvail(cur->preference)) { DOUT << "\t\tassigned the preferred register: " << tri_->getName(cur->preference) << "\n"; @@ -872,6 +873,7 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) { } else DOUT << "\t\tunable to assign the preferred register: " << tri_->getName(cur->preference) << "\n"; + } // Scan for the first available register. TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_); |