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authorOwen Anderson <resistor@mac.com>2008-07-23 19:47:27 +0000
committerOwen Anderson <resistor@mac.com>2008-07-23 19:47:27 +0000
commit50ca1a232b23265d72dc745102abd9492cff55db (patch)
tree46276e5ccb953cc67f753171431bc36d8f1436ed /lib/CodeGen/RegAllocLinearScan.cpp
parent29b19478f25ce9785682bede679bd8129b8ab5e9 (diff)
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Fix a compile-time regression introduced by my heuristic-changing patch. I forgot
to multiply the instruction count by a constant factor in a few places, which caused the register allocator to require many more iterations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53959 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocLinearScan.cpp')
-rw-r--r--lib/CodeGen/RegAllocLinearScan.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index 4df172d..ad830b2 100644
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -852,7 +852,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
// All registers must have inf weight. Just grab one!
minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
if (cur->weight == HUGE_VALF ||
- li_->getApproximateInstructionCount(*cur) == 1)
+ li_->getApproximateInstructionCount(*cur) == 0)
// Spill a physical register around defs and uses.
li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_);
}