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authorDale Johannesen <dalej@apple.com>2008-09-20 02:03:04 +0000
committerDale Johannesen <dalej@apple.com>2008-09-20 02:03:04 +0000
commitd9e4fd611933c2e32a8b1173c9ffa5133a6e18d5 (patch)
treedf3fded100e929eafbdbfd09d50b129602123914 /lib/CodeGen/RegAllocLinearScan.cpp
parentaf3c4e378b4151a3192cc83e4e886f8d28f98f17 (diff)
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Teach coalescer about earlyclobber bits.
Check bits for preferred register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56384 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocLinearScan.cpp')
-rw-r--r--lib/CodeGen/RegAllocLinearScan.cpp7
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index df9d393..5a1944f 100644
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -1122,9 +1122,12 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
unsigned FreeRegInactiveCount = 0;
// If copy coalescer has assigned a "preferred" register, check if it's
- // available first.
+ // available first. Coalescer can create new earlyclobber interferences,
+ // so we need to check that.
if (cur->preference) {
- if (prt_->isRegAvail(cur->preference) && RC->contains(cur->preference)) {
+ if (prt_->isRegAvail(cur->preference) &&
+ RC->contains(cur->preference) &&
+ noEarlyClobberConflict(cur, cur->preference)) {
DOUT << "\t\tassigned the preferred register: "
<< tri_->getName(cur->preference) << "\n";
return cur->preference;