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| author | Vikram S. Adve <vadve@cs.uiuc.edu> | 2003-05-27 00:05:23 +0000 |
|---|---|---|
| committer | Vikram S. Adve <vadve@cs.uiuc.edu> | 2003-05-27 00:05:23 +0000 |
| commit | 5f2180c53330502eb2f0f5bf3f21a838ad800906 (patch) | |
| tree | fd2e03a6e2409e48c1d145b16ebb8ff41c77003d /lib/CodeGen/RegAllocSimple.cpp | |
| parent | 49cab03c8149619b5c07e473b08d73b91aefb35c (diff) | |
| download | external_llvm-5f2180c53330502eb2f0f5bf3f21a838ad800906.zip external_llvm-5f2180c53330502eb2f0f5bf3f21a838ad800906.tar.gz external_llvm-5f2180c53330502eb2f0f5bf3f21a838ad800906.tar.bz2 | |
(1) Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.
(2) Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
and related functions and flags. Fixed several bugs where only
"isDef" was being checked, not "isDefAndUse".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6341 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocSimple.cpp')
| -rw-r--r-- | lib/CodeGen/RegAllocSimple.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index 6b95af8..31b6374 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -173,7 +173,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { // register in any given instruction unsigned physReg = Virt2PhysRegMap[virtualReg]; if (physReg == 0) { - if (op.opIsDef()) { + if (op.opIsDefOnly() || op.opIsDefAndUse()) { if (TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) { // must be same register number as the first operand // This maps a = b + c into b += c, and saves b into a's spot |