Change MachineBasicBlock's vector of MachineInstr pointers into an

ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11340 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 5 insertions, 7 deletions

diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index ac76220..a40ec64 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -150,12 +150,10 @@ void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
 
 void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
   // loop over each instruction
-  for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
+  for (MachineBasicBlock::iterator MI = MBB.begin(); MI != MBB.end(); ++MI) {
     // Made to combat the incorrect allocation of r2 = add r1, r1
     std::map<unsigned, unsigned> Virt2PhysRegMap;
 
-    MachineInstr *MI = *I;
-
     RegsUsed.resize(MRegisterInfo::FirstVirtualRegister);
     
     // a preliminary pass that will invalidate any registers that
@@ -197,11 +195,11 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
             } else {
               physReg = getFreeReg(virtualReg);
             }
-            ++I;
-            spillVirtReg(MBB, I, virtualReg, physReg);
-            --I;
+            ++MI;
+            spillVirtReg(MBB, MI, virtualReg, physReg);
+            --MI;
           } else {
-            physReg = reloadVirtReg(MBB, I, virtualReg);
+            physReg = reloadVirtReg(MBB, MI, virtualReg);
             Virt2PhysRegMap[virtualReg] = physReg;
           }
         }