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author | Evan Cheng <evan.cheng@apple.com> | 2008-04-10 23:47:53 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2008-04-10 23:47:53 +0000 |
commit | 5d3600f5766e93cb459ef6108fba00c052aa6388 (patch) | |
tree | b4682eab3c2bd2c2a38df90cf201ce0169f52501 /lib/CodeGen/RegisterScavenging.cpp | |
parent | c04575f494395412275389efbe152c8ed6129030 (diff) | |
download | external_llvm-5d3600f5766e93cb459ef6108fba00c052aa6388.zip external_llvm-5d3600f5766e93cb459ef6108fba00c052aa6388.tar.gz external_llvm-5d3600f5766e93cb459ef6108fba00c052aa6388.tar.bz2 |
Allow registers defined by implicit_def to be clobbered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49512 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegisterScavenging.cpp')
-rw-r--r-- | lib/CodeGen/RegisterScavenging.cpp | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp index c71d3be..1d9effb 100644 --- a/lib/CodeGen/RegisterScavenging.cpp +++ b/lib/CodeGen/RegisterScavenging.cpp @@ -55,22 +55,28 @@ static bool RedefinesSuperRegPart(const MachineInstr *MI, } /// setUsed - Set the register and its sub-registers as being used. -void RegScavenger::setUsed(unsigned Reg) { +void RegScavenger::setUsed(unsigned Reg, bool ImpDef) { RegsAvailable.reset(Reg); + ImplicitDefed[Reg] = ImpDef; for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); - unsigned SubReg = *SubRegs; ++SubRegs) + unsigned SubReg = *SubRegs; ++SubRegs) { RegsAvailable.reset(SubReg); + ImplicitDefed[SubReg] = ImpDef; + } } /// setUnused - Set the register and its sub-registers as being unused. void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) { RegsAvailable.set(Reg); + ImplicitDefed.reset(Reg); for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) - if (!RedefinesSuperRegPart(MI, Reg, TRI)) + if (!RedefinesSuperRegPart(MI, Reg, TRI)) { RegsAvailable.set(SubReg); + ImplicitDefed.reset(SubReg); + } } void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { @@ -86,6 +92,7 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { if (!MBB) { NumPhysRegs = TRI->getNumRegs(); RegsAvailable.resize(NumPhysRegs); + ImplicitDefed.resize(NumPhysRegs); // Create reserved registers bitvector. ReservedRegs = TRI->getReservedRegs(MF); @@ -216,6 +223,7 @@ void RegScavenger::forward() { setUnused(ChangedRegs); // Process defs. + bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); @@ -240,12 +248,13 @@ void RegScavenger::forward() { if (RedefinesSuperRegPart(MI, MO, TRI)) continue; - // Implicit def is allowed to "re-define" any register. + // Implicit def is allowed to "re-define" any register. Similarly, + // implicitly defined registers can be clobbered. assert((isReserved(Reg) || isUnused(Reg) || - MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF || + IsImpDef || isImplicitlyDefined(Reg) || isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) && "Re-defining a live register!"); - setUsed(Reg); + setUsed(Reg, IsImpDef); } } |