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author | Benjamin Kramer <benny.kra@googlemail.com> | 2010-12-22 23:17:45 +0000 |
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committer | Benjamin Kramer <benny.kra@googlemail.com> | 2010-12-22 23:17:45 +0000 |
commit | f50125ecaab0cc379892280de33f0a2d387f7f5b (patch) | |
tree | 0d93b7f2f1e721b6081b3c140a773ae14aded3ef /lib/CodeGen/SelectionDAG/DAGCombiner.cpp | |
parent | 4ac19470dc26decba85f5bf4dd7e6edb54d77152 (diff) | |
download | external_llvm-f50125ecaab0cc379892280de33f0a2d387f7f5b.zip external_llvm-f50125ecaab0cc379892280de33f0a2d387f7f5b.tar.gz external_llvm-f50125ecaab0cc379892280de33f0a2d387f7f5b.tar.bz2 |
DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is illegal. The latter usually compiles into smaller code.
example code:
unsigned foo(unsigned x, unsigned y) {
if (x != 0) y--;
return y;
}
before:
_foo: ## @foo
cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01]
sbbl %eax, %eax ## encoding: [0x19,0xc0]
notl %eax ## encoding: [0xf7,0xd0]
addl 8(%esp), %eax ## encoding: [0x03,0x44,0x24,0x08]
ret ## encoding: [0xc3]
after:
_foo: ## @foo
cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01]
movl 8(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08]
adcl $-1, %eax ## encoding: [0x83,0xd0,0xff]
ret ## encoding: [0xc3]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122455 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
-rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index e4f3027..7de66f6 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1443,6 +1443,15 @@ SDValue DAGCombiner::visitADD(SDNode *N) { } } + // add (sext i1), X -> sub X, (zext i1) + if (N0.getOpcode() == ISD::SIGN_EXTEND && + N0.getOperand(0).getValueType() == MVT::i1 && + !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { + DebugLoc DL = N->getDebugLoc(); + SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); + return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); + } + return SDValue(); } |