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| author | Evan Cheng <evan.cheng@apple.com> | 2011-08-30 19:09:48 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-08-30 19:09:48 +0000 |
| commit | 37fefc20d3a1e3934a377567d54a141f67752227 (patch) | |
| tree | bce1070e7fb576ec47876c47930becf0c3a15f01 /lib/CodeGen/SelectionDAG/InstrEmitter.cpp | |
| parent | 6e4be237b076168167ad21d7cb46a70c17c59f5f (diff) | |
| download | external_llvm-37fefc20d3a1e3934a377567d54a141f67752227.zip external_llvm-37fefc20d3a1e3934a377567d54a141f67752227.tar.gz external_llvm-37fefc20d3a1e3934a377567d54a141f67752227.tar.bz2 | |
Follow up to r138791.
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/InstrEmitter.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 568f66c0..1e45ec6 100644 --- a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -761,6 +761,10 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, i != e; ++i) MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI); } + + // Run post-isel target hook to adjust this instruction if needed. + if (II.hasPostISelHook()) + TLI->AdjustInstrPostInstrSelection(MI, Node); } /// EmitSpecialNode - Generate machine code for a target-independent node and |