Add selection DAG nodes for subreg insert/extract. PR1350

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40516 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 17 insertions, 1 deletions

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 25f0320..4131ed9 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -957,7 +957,23 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       AddLegalizedOperand(SDOperand(Node, i), Tmp1);
     }
     return Tmp2;
-        
+   case ISD::EXTRACT_SUBREG: {
+      Tmp1 = LegalizeOp(Node->getOperand(0));
+      ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
+      assert(idx && "Operand must be a constant");
+      Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
+      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+    }
+    break;
+  case ISD::INSERT_SUBREG: {
+      Tmp1 = LegalizeOp(Node->getOperand(0));
+      Tmp2 = LegalizeOp(Node->getOperand(1));      
+      ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
+      assert(idx && "Operand must be a constant");
+      Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
+      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
+    }
+    break;      
   case ISD::BUILD_VECTOR:
     switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
     default: assert(0 && "This action is not supported yet!");