Add support for vicmp/vfcmp codegen, more legalize support coming.

This is necessary to unbreak the build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50988 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 26 insertions, 0 deletions

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index dcdc554..1892e8a 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2886,6 +2886,24 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       break;
     }
     break;
+  case ISD::VSETCC: {
+    Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
+    Tmp2 = LegalizeOp(Node->getOperand(1));   // RHS
+    SDOperand CC = Node->getOperand(2);
+    
+    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
+
+    // Everything is legal, see if we should expand this op or something.
+    switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
+    default: assert(0 && "This action is not supported yet!");
+    case TargetLowering::Legal: break;
+    case TargetLowering::Custom:
+      Tmp1 = TLI.LowerOperation(Result, DAG);
+      if (Tmp1.Val) Result = Tmp1;
+      break;
+    }
+    break;
+  }
 
   case ISD::SHL_PARTS:
   case ISD::SRA_PARTS:
@@ -6875,6 +6893,14 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
     }
     break;
   }
+  case ISD::VSETCC: {
+    SDOperand LL, LH, RL, RH;
+    SplitVectorOp(Node->getOperand(0), LL, LH);
+    SplitVectorOp(Node->getOperand(1), RL, RH);
+    Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
+    Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
+    break;
+  }
   case ISD::ADD:
   case ISD::SUB:
   case ISD::MUL: