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| author | Stephen Hines <srhines@google.com> | 2012-09-10 16:47:31 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2012-09-10 16:47:31 -0700 |
| commit | 1c4ad5ef4fab105f0c8af7edd026e00502fb6279 (patch) | |
| tree | cb5bdfd58f776d00be450d0a5585f8f0186585da /lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | |
| parent | d62cdbe700ab288e9ad447824066edb7d17167d9 (diff) | |
| parent | 1dc2591e9ef0730612902f94976ce85bed6859de (diff) | |
| download | external_llvm-1c4ad5ef4fab105f0c8af7edd026e00502fb6279.zip external_llvm-1c4ad5ef4fab105f0c8af7edd026e00502fb6279.tar.gz external_llvm-1c4ad5ef4fab105f0c8af7edd026e00502fb6279.tar.bz2 | |
Merge branch 'upstream' into merge-2012_09_10
Conflicts:
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
lib/Support/DynamicLibrary.cpp
lib/Support/LockFileManager.cpp
Change-Id: I91e94c3a7a76e19c688307c5a480a640a3bd2b7e
Diffstat (limited to 'lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index bf0a437..2b86e36 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -656,6 +656,8 @@ void ScheduleDAGRRList::EmitNode(SUnit *SU) { break; case ISD::MERGE_VALUES: case ISD::TokenFactor: + case ISD::LIFETIME_START: + case ISD::LIFETIME_END: case ISD::CopyToReg: case ISD::CopyFromReg: case ISD::EH_LABEL: @@ -1756,6 +1758,7 @@ public: return V; } +#ifndef NDEBUG void dump(ScheduleDAG *DAG) const { // Emulate pop() without clobbering NodeQueueIds. std::vector<SUnit*> DumpQueue = Queue; @@ -1766,6 +1769,7 @@ public: SU->dump(DAG); } } +#endif }; typedef RegReductionPriorityQueue<bu_ls_rr_sort> @@ -1893,6 +1897,7 @@ unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const { //===----------------------------------------------------------------------===// void RegReductionPQBase::dumpRegPressure() const { +#ifndef NDEBUG for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), E = TRI->regclass_end(); I != E; ++I) { const TargetRegisterClass *RC = *I; @@ -1902,6 +1907,7 @@ void RegReductionPQBase::dumpRegPressure() const { DEBUG(dbgs() << RC->getName() << ": " << RP << " / " << RegLimit[Id] << '\n'); } +#endif } bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const { |