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author | Evan Cheng <evan.cheng@apple.com> | 2008-03-11 07:19:34 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2008-03-11 07:19:34 +0000 |
commit | 676dd7c80b6f91178452535ac45ca58feb23cc42 (patch) | |
tree | 33282790f7a542b3ef2f3af7a23646d8f8514a1c /lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | |
parent | 204496d58e7e740f0da6d41c6214a91d67950d26 (diff) | |
download | external_llvm-676dd7c80b6f91178452535ac45ca58feb23cc42.zip external_llvm-676dd7c80b6f91178452535ac45ca58feb23cc42.tar.gz external_llvm-676dd7c80b6f91178452535ac45ca58feb23cc42.tar.bz2 |
When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48218 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp')
-rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index df57f74..0d3926f 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -768,7 +768,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { // Issue expensive cross register class copies. MVT::ValueType VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII); const TargetRegisterClass *RC = - TRI->getPhysicalRegisterRegClass(VT, Reg); + TRI->getPhysicalRegisterRegClass(Reg, VT); const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); if (!DestRC) { assert(false && "Don't know how to copy this physical register!"); |