Revert 72707 and 72709, for the moment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 0 insertions, 7 deletions

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index e509372..7aa15bc 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -268,13 +268,6 @@ unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) {
   unsigned N = Node->getNumOperands();
   while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
     --N;
-  // Skip hard registers set as a side effect (i.e. not result 0).
-  while (N && Node->getOperand(N - 1).getOpcode() == ISD::CopyToReg &&
-         Node->getOperand(N-1).getResNo() != 0 &&
-         !TargetRegisterInfo::isVirtualRegister(
-                dyn_cast<RegisterSDNode>(Node->getOperand(N-1).getOperand(1))
-                ->getReg()))
-    --N;
   if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
     --N; // Ignore chain if it exists.
   return N;