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| author | Dan Gohman <gohman@apple.com> | 2009-01-15 16:58:17 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-01-15 16:58:17 +0000 |
| commit | a0c429eecdba4926d61591f84e73c8d473715e3a (patch) | |
| tree | 3001c878835f6f2c17fae20fcac7bf27388a29db /lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp | |
| parent | 0275b138ada11dd70e02f6fc56829304ab7a0559 (diff) | |
| download | external_llvm-a0c429eecdba4926d61591f84e73c8d473715e3a.zip external_llvm-a0c429eecdba4926d61591f84e73c8d473715e3a.tar.gz external_llvm-a0c429eecdba4926d61591f84e73c8d473715e3a.tar.bz2 | |
More consts on TargetLowering references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62262 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index 5740cc9..60a4f61 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -380,7 +380,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, MVT ValueVT, ISD::NodeType AssertOp = ISD::DELETED_NODE) { assert(NumParts > 0 && "No parts to assemble!"); - TargetLowering &TLI = DAG.getTargetLoweringInfo(); + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); SDValue Val = Parts[0]; if (NumParts > 1) { @@ -525,7 +525,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, static void getCopyToParts(SelectionDAG &DAG, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { - TargetLowering &TLI = DAG.getTargetLoweringInfo(); + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); MVT PtrVT = TLI.getPointerTy(); MVT ValueVT = Val.getValueType(); unsigned PartBits = PartVT.getSizeInBits(); @@ -648,8 +648,7 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val, // Handle a multi-element vector. MVT IntermediateVT, RegisterVT; unsigned NumIntermediates; - unsigned NumRegs = - DAG.getTargetLoweringInfo() + unsigned NumRegs = TLI .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, RegisterVT); unsigned NumElements = ValueVT.getVectorNumElements(); @@ -4819,7 +4818,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, /// processed uses a memory 'm' constraint. static bool hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos, - TargetLowering &TLI) { + const TargetLowering &TLI) { for (unsigned i = 0, e = CInfos.size(); i != e; ++i) { InlineAsm::ConstraintInfo &CI = CInfos[i]; for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) { |