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author | Evan Cheng <evan.cheng@apple.com> | 2010-05-20 06:13:19 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2010-05-20 06:13:19 +0000 |
commit | 15a16def6e70c8f7df1023da80ceb89887203b40 (patch) | |
tree | 8c2637a4d2816e5442916d246406ee41dfb3ced0 /lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | |
parent | 761fd4c1d97977c16de9f0cf921056a37b906304 (diff) | |
download | external_llvm-15a16def6e70c8f7df1023da80ceb89887203b40.zip external_llvm-15a16def6e70c8f7df1023da80ceb89887203b40.tar.gz external_llvm-15a16def6e70c8f7df1023da80ceb89887203b40.tar.bz2 |
Add a hybrid bottom up scheduler that reduce register usage while avoiding
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104216 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp')
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 76e09e7..6d789a6 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -134,9 +134,11 @@ namespace llvm { return createFastDAGScheduler(IS, OptLevel); if (TLI.getSchedulingPreference() == Sched::Latency) return createTDListDAGScheduler(IS, OptLevel); - assert(TLI.getSchedulingPreference() == Sched::RegPressure && + if (TLI.getSchedulingPreference() == Sched::RegPressure) + return createBURRListDAGScheduler(IS, OptLevel); + assert(TLI.getSchedulingPreference() == Sched::Hybrid && "Unknown sched type!"); - return createBURRListDAGScheduler(IS, OptLevel); + return createHybridListDAGScheduler(IS, OptLevel); } } |