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| author | Evan Cheng <evan.cheng@apple.com> | 2010-02-19 00:34:39 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-02-19 00:34:39 +0000 |
| commit | 7ef91d5d2ed4129318c2e297cac5601bbc8c0c75 (patch) | |
| tree | f2d7f0829e8f14fb19a76ee971e7f1da69f75f0c /lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | f7f5da39d94e150dc4e13068de44185c9fa06700 (diff) | |
| download | external_llvm-7ef91d5d2ed4129318c2e297cac5601bbc8c0c75.zip external_llvm-7ef91d5d2ed4129318c2e297cac5601bbc8c0c75.tar.gz external_llvm-7ef91d5d2ed4129318c2e297cac5601bbc8c0c75.tar.bz2 | |
Transform (xor (setcc), (setcc)) == / != 1 to
(xor (setcc), (setcc)) != / == 1.
e.g. On x86_64
%0 = icmp eq i32 %x, 0
%1 = icmp eq i32 %y, 0
%2 = xor i1 %1, %0
br i1 %2, label %bb, label %return
=>
testl %edi, %edi
sete %al
testl %esi, %esi
sete %cl
cmpb %al, %cl
je LBB1_2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96640 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 9f9d8b0..2cb4fc9 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1855,9 +1855,19 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, SDValue Op0 = N0; if (Op0.getOpcode() == ISD::TRUNCATE) Op0 = Op0.getOperand(0); - if (Op0.getOpcode() == ISD::AND && - isa<ConstantSDNode>(Op0.getOperand(1)) && - cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { + + if ((Op0.getOpcode() == ISD::XOR || Op0.getOpcode() == ISD::AND) && + Op0.getOperand(0).getOpcode() == ISD::SETCC && + Op0.getOperand(1).getOpcode() == ISD::SETCC) { + // (and (setcc), (setcc)) == / != 1 -> (setcc) == / != (setcc) + // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) + if (Op0.getOpcode() == ISD::XOR) + Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; + return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), + Cond); + } else if (Op0.getOpcode() == ISD::AND && + isa<ConstantSDNode>(Op0.getOperand(1)) && + cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { if (Op0.getValueType() != VT) Op0 = DAG.getNode(ISD::AND, dl, VT, DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), |