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authorDale Johannesen <dalej@apple.com>2010-04-20 22:34:09 +0000
committerDale Johannesen <dalej@apple.com>2010-04-20 22:34:09 +0000
commit9413edc0257abc50efe873d949163718a0a3832c (patch)
tree51ea6891b55970e100d8b3e93ddbd4985886567a /lib/CodeGen/SelectionDAG/TargetLowering.cpp
parentdc433dba32a2421e6c0deab9fcf87b9026c9bbd0 (diff)
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Because of the EMMS problem, right now we have to support
user-defined operations that use MMX register types, but the compiler shouldn't generate them on its own. This adds a Synthesizable abstraction to represent this, and changes the vector widening computation so it won't produce MMX types. (The motivation is to remove noise from the ABI compatibility part of the gcc test suite, which has some breakage right now.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101951 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/TargetLowering.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 11dca39..5c3992e 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -720,7 +720,7 @@ void TargetLowering::computeRegisterProperties() {
unsigned NElts = VT.getVectorNumElements();
for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
EVT SVT = (MVT::SimpleValueType)nVT;
- if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
+ if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT &&
SVT.getVectorNumElements() > NElts && NElts != 1) {
TransformToType[i] = SVT;
ValueTypeActions.setTypeAction(VT, Promote);