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authorChris Lattner <sabre@nondot.org>2009-04-12 07:46:30 +0000
committerChris Lattner <sabre@nondot.org>2009-04-12 07:46:30 +0000
commit36e3946ac2f30a0bda66538ef2b974b1c8fbdc97 (patch)
treecdfddb34600ca2c2ee2fef89360da592e93ed847 /lib/CodeGen/SelectionDAG
parentc5040ab6065d5c569a1af0848b6e672b22b174b7 (diff)
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make UpdateValueMap handle the possiblity that we could be
copying into the right register, avoiding a copy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68889 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG')
-rw-r--r--lib/CodeGen/SelectionDAG/FastISel.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 7e30053..251e96a 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -158,7 +158,7 @@ unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
unsigned &AssignedReg = ValueMap[I];
if (AssignedReg == 0)
AssignedReg = Reg;
- else {
+ else if (Reg != AssignedReg) {
const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
Reg, RegClass, RegClass);